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: , ( ) . (IF) (CASE). . , : bit,bit_vector,std_logic_vector. . exampale1, , VHDL..
( ) . VHDL. , . : , .
, , . PROCESS (IF) (CASE). (<=WHEN).
D "", .
ENTITY d_ff ISentity declaration
PORT (d,c,r:IN BIT;-port statement q:INOUT BIT);
END d_ff;
ARCHITECTURE one OF d_ff IS
architecture "one" of entity d_ff
BEGIN
beh_tr: BLOCK(c='1' OR r='1');
BEGIN
q<=GUARDED '0' WHEN r ='1'
ELSE d WHEN c='1' AND NOT c'STABLE
ELSE q;
END BLOCK beh_tr;
END one;
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VHDL-, , , 1. , , y x ntit , , -.
(s<=s0) , WAIT. , p_clk, p_clk .
, p_clk, _lk.
p_clk'stable . ( ).
"not p_clk'stable " , , . , , , Wait.
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8.1 8.2
1
TYPE state IS (s0,s1,s2);
Y input IS (x0,x1);
TYPE output IS (y0,y1,y2);
SIGNAL x: INPUT;
SIGNAL y_out:OUTPUT;
..
PROCESS
SIGNAL s:state;
BEGIN
s<=s0;
LOOP
WAIT UNTILI (p_clk='1' AND NOT p_clk'stable);
CASE s IS
WHEN s0=>IF x=x0 THEN s<=s0;
ELSEIF(x=x1) THEN s<=s1;
ELSE s<=s2;
END IF;
WHEN s1=>IF x=x0 THEN s<=s1;
ELSEIF x=x1 THEN s<=s2;
ELSE s<=s0;
END IF;
WHEN s2=>IF x=x0 THEN s<=s2;
ELSEIF x=x1 THEN s<=s3;
ELSE s<=s1;
END IF;
WHEN s3=>IF x=x0 THEN s<=s3;
ELSEIF x=x1 THEN S<=s0;
ELSE s<=s2;
END IF;
END CASE;
--
IF (s=s3 AND x=x1) THEN y<=y1;
ELSEIF(s=s0 AND x=x2) THEN y<=y2;
ELSE y<=y0;
END IF;
END LOOP;
END PROCESS;
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, VHDL .
