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- ("Xilinx","Altera",AMD .) :"Synopsys","Cadence","VievLogic" . ( "Xilinx" " Altera ") .

( ), . - .

. 1990- . . c , . 1990- . . . EDIF 2.0.0 3.0.0. ( VHDL, Verilong . .).

1990- . . ; , ; , . , , - , , .

Xilinx - Foundation 1.4 1.5, Xilinx, Aldec Synopsys. Altera , VHDL, Verilong HDL FPGA express Synopsys, Model Sim Model Technology ( Mentor Graphics. , ( ) , -, . , (, , , ). ViewLogic D. , , WorkView Office ViewLogic.

WorkView Office ( , W'95,98 NT), . WorkView Office - ( ), , . , (, ), . , (, ), , .

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, , .

(-) PSpise A/D, Design Lab. (, i- "Spectrum Software"). "Micro Sim" Design Lab 8.0 , - , . , , CPLD FPGA , , , .

, ( -) () , Micro Sim, ViewLogic OrCAD.

. , , , . ( ) "Synopsys", "Cadence"( , ).

. 90% (. . ), ( ) . , , "Exemplar Logic","Symplicity" , VHDL Verilog HDL, , ( ).

. ( -) , , . , , , . , QUARTUS "Altera" : , / . Signal Tap Logic Analysis , , , JTAG , .

, , , +FG, 5 S ( ) "Triscend". - ( S 52) ( FPGA), . , , Triscend FastChip.

, , "Atmel", I FPGA.

SOPC, Generic, (, "Altera"), - ( 8- S 8052 32- RISC-) , . , - +PLUSII, .

. . (, VHDL, Verilong EDIF). (, , ).

 





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