(if Statement)
.
< if_Statement>::=IF<>THEN <_>
{ELSIF<>THEN <_ >}
[ELSIF<_>]
END IF;
If . .
(Case Statement)
.
<Case_Statement>::=CASE<>IS
WHEN<>=><_>
{ WHEN <>=>< >}
END CASE;
<>::=<_>|<_>
| <__>|<..>
. . , . - .
(Loop Statement)
.
< Loop_Statement>::=[<_>:][WHILE<>|
FOR<>IN <_>]
LOOP<_>
END LOOP[<_>];
. ( ). , .
NEXT I.
<Next_Statement>::=NEXT[<_>][WHEN<>];
.
<Exit_Statement>::=EXIT[<_>][WHEN<>];
.
(Call Procedure Statement) (Return Statement)
. (Call Procedure Statement).
<Call_Procedure_Statement>::=<_>[(<_>)]
(Return Statement).
<Return_Statement>::=RETURN[<>];
(Assert Statement)
.
<Assert Statement>::=[<>:]ASSERT<> [REPORT<>]
[SEVERITY <_>]
<_>::=NOTE|WARNING|ERROR|FAILURE
, , , .
|
|
|
, "Assertion violation". .
VHDL , VHDL
. VHDL , =not(not(in1^in2)^in3) exemple1, 2-. . 8.11.
:
ENTITY example1 IS
R (in1, in2, in3: IN BIT;
y:OUT BIT;
END example1;
ARCHITECTURE struct OF example1 IS
COMPONENT nand2
R (x1, x2: IN BIT;q: OUT BIT);
ND N;
SIGNAL z: I;
GIN
Unit1: nand2 R (i1, in2,z);
Unit2: nand2 R (q=>y, 1=>in3, 2=>z);
END struct;
, , , nand2. ,
2-, :
|
NIY nand2 IS
R (in1, in2: IN I;
out:OUT BIT;
END nand2;
ARCHITECTURE behave OF nand2 IS
BEGIN
Out<=not(in1 and in2);
END behave;
nand2 unit1 unit2 in1, in2, in3 Y () Z. unit1 . unit2 . N.
16- , Component Generate., D , .
NIY reg16 IS
R (input: IN bit_VECTOR(0 TO 15);
clock: IN I;
output: OUT BIT VEKTOR(0 TO 15);
END reg16;
ARCHITECTURE struct OF reg16 IS
NN dff
R (d, clk: IN BIT; q: OUT BIT);
END NN;
BEGIN
g1: FOR i IN 1 TO 16 GENERATE
dff PORT MAP(input(i), clock, output(i));
END GENERATE g1;
Generate.
. Entity Declaration, :
ENTITY input3_nand IS-entity declaration
R (in1, in2, in3: IN BIT; - port statement
y:OUT BIT);
END input3_orand1;
ARCHITECTURE one OF input3_nand IS
-architecture "one" of entity input3_nand1
|
|
|
BEGIN
nand3:PROCESS
BEGIN
IF (in3='1') THEN y<=NOT (in1 AND in2);
ELSE y<='1';
END IF;
WAIT ON in1, in2, in3;
END PROCESS;
END;
8- ( ) :
Synch_count: PROCESS
BEGIN
WAIT UNTIL clock='1';
IF(reset='1') N count<="00000000";
ELSE count <= count+'1';
END IF;
END PROCESS;
, , (). :
, ;
(), ;
, .
, , , . .
, - , . , , ( ), . , , VHDL-, , , , . , .
- . ( ) ( ) .
. , . , , , .
