- . . , : , , , - , , , , .
( ) ,
. :
(Process Statement);
(Block Statement);
(Condition Signal Assignment Statement);
(Selected Signal Assignment Statement);
(Procedure Call Statement);
(Assert Statement);
( ) (Component Instantiation Statement) . .
, .
. ( ) , , , . , . : , , () , , ( , ).
( )
<Architecture_Declaration>::=
ARCHITECTURE<_ _>OF<_>IS
|
|
|
[{SIGNAL<_>:<>;}]
[{COMPONENT<__>
[GENERIC(<_>);]
[PORT(<__>:IN<>);
<__>: OUT<>;]
END COMPONENT;}]
BEGIN
[{<_>:< __>
[GENERIC (<_>);]
RT (< >);]
[<_>]
END [<__>];
.
.
<Component_Instantiation_Statement>::=
<_>: <_ >
[GENERIC (<_>)]
[PORT (< >)];
, . , (=>).
( ) .
- (Block Statement)
.
< Block_Statement>::=
<_>: L [(<_>)]
[GENERIC (<__>);]
[GENERIC (<_>);]
R (<_>);
R (<_>);
<_>;
BEGIN
<_>
END BLOCK <_>;
, . () . . . .
: ; ; , ; ; ; ; ; ; . ( GUARDED) .
, , .
(Generate Statement)
.
<Generate_Statement>::=<>: FOR<>IN<>GENERATE
| IF<> GENERATE
< >
END GENERATE[<>]
. FOR IF . FOR IF, : .
|
|
|
, . , .
(Process Statement)
.
< Process_ Statement>::=[<_>] PROCESS
[<_>]
<_>
BEGIN
<__>
END PROCESS[<_>]
, . . , - , , WAIT. , . ( ).
(Wait Statement)
.
<Wait_Statement>::=WAIT [ON (<_>)]
[ UNTIL<_ >] [FOR<_>]
( ) . , ().
, , , , . .
(Signal Assignment Statement)
.
< Signal_Assignment_Statement >::=<_><=[TRANSPORT]
{<>[AFTER<>] | NULL[AFTER<>]}
( ), , , , . . <> () . , ( FR).
, . . .
|
|
|
, . , VHDL ( ) , . . - (, ), . , , , . , , ( ) .
(Conditional Signal Assignment Statement)
.
<Conditional_Signal_Assignment_Statement>::=
<_><=[QUARDED][TRANSPORT]
{<>WHEN<>ELSE}<>
(TRANSPORT) . "" (TRANSPORT) , .
( ) .
.
<>::= <_>{<_>}
<_>::=<__>
[AFTER<__>].
(Selected Signal Assignment Statement)
.
<Selected_Signal_Assignment_Statement >::=
[<>:]WITH<>SELECT
{<_><= [QUARDED][TRANSPORT]
{<> WHEN<>;<>WHEN<>;
(Call Procedure Statement)
.
<Call_Procedure_Statement>::=
[<>:]<_>[(<__>)].
VHDL, , , . . , , . .
(Assert Statement)
.
< Assert_Statement>::=[<>:]ASSERT <> [REPORT<>]
[SEVERITY<_>]
<_>::=
NOTE | WARNING | ERROR | FAILURE
, , . , .
