7.4.1. FPGA
(FPGA ) . . , . , - . FPGA . , , /, FPGA , FPGA / , 20.
FPGA .
() (granularity). . - n-, -. , . FPGA .
FPGA :
;
( LUT- Look-Up Tables).
FPGA , , , , - . 0 1 2n - 1 , . 7.11, . , 10 = 00 DO . F(0), . 10 = 01 D1, D1 = F(1), . . n .
FPGA , (2-1,4-1), .
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FPGA - (LUTs). . . , , , m , . . (. 7.11, ) .
FPGA , , . , , . () , ( R ). , RC, , .
- , ( ), . , . , , FPGA Xilinx (General Purpose Interconnects) , , (Direct Connects) (Long Lines), .
. 7.12, FPGA , .
( , , ). . , .
, / , , . . 7.12, . , - , , , . 7.12, . , .
FPGA . 7.13 4000 Xilinx. ( ) ( ), , . . .
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, .
7.4.2. FPGA XILINX
FPGA XC4000E Xilinx (. 7.14) . Xilinx FPGA, 30-40% , FPGA .
, . 7.14 , .
: G, F . G F 16 1 . 1 2 G F ( 8 1) , . , 1 2, 1 2 . DIN. , G F, 1 .
, Y 4 G , X 6 - F .
: ( ), , ( ).
3 5 DIN.
7 8, , . (Enable Clock) . 9 10 , .
SD (Set Direct) RD (Reset Direct), S/R SR, , , 1-4. 1-4 ( ).
/ 4000 (. 7.15) - . , 7 4.
1 , -. R , . R . U/D (Up/Down). 1 SLR (Slew Rate). , SLR. , , , .
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( 1 , 2 ), , , . / (, / ). (CLKI) (CLKO) . , (Output), .
2 8. , .
