, . , , , . , . , , . .
, , ( antifuse, - , , ). , , . . 7.9, , R Rn, U = Ucc R /(R + Rnp). Rnp R R R R. U ( ) " , U U .
, . (. 7.9, ) , ( ef) F -,b, d. , . (. 7.9, ) . f . 2-1 , . 7.9, . , .
. 7.1.2 , CPLD -, . FPGA
(SLC, Small Logic Cells), (LUTs, Look-Up Tables). () , , FPGA, CPLD.
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, , .
1. . CPLD, (SOP). , F . , , . 2, , - λ 1 (. 7.10, ). . , 2 F = F* 0 = F*. , . , Ucc, . . F = F* 1 = F*.
2. . . . , , . , , n , + n n + , m + n + .
, ( 7.10, ). 1 (Output Enable 1) 1 , F ( - ). 1 , 2 2, . 2 . 1 2 , .
1 , , :
, 1 0;
, 1 1, 2 2;
, , 1 1.
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3. . - ( ) , . D . D (. 7.10, ) 2 1.
D, D, F. 1 , F = 0 Q, . . , F= 1 - , . . . , -, F.
D , JK, RS ( ).
(combinatorial) (registered). . . 7.10, , 2 , F , R ( ).
. , .
7.3.2. ,
, . () .
. , , - EPROM EEPROM. 5 , 3,3; 2,5; 1,8 1,6 . , , .
. ( , . . , ). , . , . ( ). (, , , , , , . .).
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, , .
Turbo bit, , /.
JTAG. () , , , JTAG , .
. , , In-System Programmable (ISP). ISP (, ISP, , ). , SRAM-based . ISP , , , . , , .
. . .
. , , . , , , . SLC (Slew Rate Control) . , , , . (. . ).