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Functionand(xl,x2:bit) returnboolean is begi n




return (xl and x2) ='1'; end;

, if, :

Variablea,b,c: bit; if (a and b and c) then

* * ■

end if; boolean.


-, , . wait , , , .

, . VHDL , , , . . . : - , , , , .

:

\ 1 \ .

.

:

' left - . ' right - . T'high - . ' low - . T'image(x) - . T'value(x) - . T'pos(x) - . T'val () - X.

:

type st is (one,two,three);

st'right = three, st'pos(three) = 2, st'val(l) = two. positive'low * 1, positive'high =2147483647. integer'valueC'LOOO") =1000, integer'image(330) ="330".


:

A'left[(N)] - N- .

A' right[(n)] - N- .

Afhigh[(N)] - N- .

' 1 cw [ (n) ] - N- .

A' range[(N)] - N- .

A' reverse_range[(N)] - N- .

A' length[(N)] - N- .

A'ascending[(N)] - , true, He-N- - .

:

type s2 is array(2 downto 1, 0 to 3) of integer;

S2'left(l) - 2, s2'right(2) - 3,

S2'high(l) * 2, s2'low(2) = 0,

s2'range(2) = 0 to 3, s2'reverse_range(l)- 1 to 2,

S2'length(2) = 4.

s:

S' stable [CO] - , true, S.

S'transaction - bit, , S.

s'event - , true, S .

sfactive - , true, s .

S'last_value - , S, s ,

, .


Process(CLK) begin

if CLK='l' and CLK'event then-- D-

ql<=al;
end if;
if not CLK'stable then -- D-

q2<=a2; end if; if CLK'last_value /= CLK then-- D-

q3<=a3;
end if;
if CLK'active -- D-

q4<=a4;
end if;
q5<=CLK'transaction; -

end process;

, . : , - , , , , .. .. , . .

, :

\ : :=attribute \\: \ \

\\ - , , string, positive, time.

:

: :=attribute \\ of \ [{ \}] | others I all: \ \ is \\ \ \::= ((\\ |\ \

| \ \) [\\]) \ \: :- entity|architecture|configuration| package I procedure|function[type 1 subtype[ constant|si gnal jvari able | f i 1 e |component| label (literal |units I group

\\ - , , \ \ - , ,\\ -


, , , , . .

. - . , , - . :

type \\ is (\\ \,\\,\.\); attribute enum_encoding: string;

attribute enunuencoding of \\: type is "000 001 010 100";

foreign

foreign , . , . , .

VHDL

VHDL . - . , , , . , .

, : , ( ), , . . .VHD. .

:


\ \::= [\ 1ibrary\]

[\ use\]

\ \

\ \

[\ \] [\ library\]::= library \\ {, \\};

- , . . use , . . (elaboration) .

, , .. . :

\ \::= entity \\ is

["(\ \

{; \ \});] [port (\ \ { \});]

{\ \} [begin

{\ assert\ | \ \

| \ \ }] end [entity][\\];

\\ - . . . generic , , , , .

: , , , , , , , , use.

, begin, , , .. .


. - , , , generic. , -, , .. , assert .

RS-:

entity RS_FF is

generic(delay:time); port(R, S: in bit;

Q: out bit:='0'; nQ: out bit:='l'); begin

assert (R and S) /='1' report" in rs_ff r=s=1" severity error; end entity RS_ff;

delay , , , . R,S in, Q,nQ - out. , .. RS- , assert .

, , . :

\ \::= architecture \\ of \ \ is

{\ 6\} begin

{ \ \} end [architecture][\\];

. , . , . , , . : , , , , , , , ,


use, . , , .

, , , . - , - . , , - , .

RS-:

architecture behav of rs_ff is begin

processes,R)

variable qi: bit; begin

if S^'l' then

qi:='l'; elsif R='l' then

qi:='0'; end if;

Q<=qi after delay; nQ<=not qi after delay; end process; end architecture behav;

, . generic, .

, , . :

\ ::= component \\ [is] ['(\ \

{; \ \});] [port (\ \ { \});] end component [\\];


, . , . , . , , library. , , WORK.

:

\ \::= package \\ is

{ } end [package][\\];

, , , , , , , , , use.

, . , . .. , - .

. (deferred). , . .

, , , , , :

signal my_bit: IEEE.std_logic_1164.x0lZ;

, . . :


\ \::= package body \\ is

{ } end [package body][\\];

, , .

, .

package short_boolean is

constant bO:boolean:=false; false constant bl:boolean:=true; -- true function b(x:bit) return boolean; bit boolean function "not "(x:bit) return boo7ean; not, and, or function "and"(xl,x2:bit) return boolean; function Mor"(xl,x2:bit) return boolean; end package; package body short_boolean is





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