Variablet:integer; begin
Ifxl>x2 then
Return; else
t:=xl; xl:=x2; x2:=t; end if; end procedure; begin
bl:*al; 2:=2; :=; Sort2(b2,b3); Sort2(bl,b2); Sort2(b2,b3); cl<=bl; 2<=2; c3<=b3; end process;
Sort2 xl,x2, . return . .
.
procedure And4(variable xl,x2,x3,x4:in bit: = '; signal y:out bit) is begin y<=xl and x2 and x3 and x4; end procedure;
:
And4(al,a2,a3,open,b);
, open '1*.
. .
. , . , 'delayed,'stable,'quiet 'transaction, . , . , .
, , VHDL , , . , .
:
\::=[pure|impure] function \ \ |\ \ [(\ \)] return \ is {\ \} begin
^ \} return \\; end [function][\ \];
- , , "+", - , ,
out inout . return . , . return, .
, , . VHDL , .. . . . ,
|
|
|
function Bit_To_int(x:bit_vector) return natural is variable t, j:integer:=0; begin
for I in x'reverse_range loop if (x(i)='l') then
t:=t + 2**j; end if;
end loop; return t; end function Bit_To_int;
. 'reverse_range , . , - bit_vector(7 downto 0), 0 to 7. , , -.
pure impure . , . , - , , . .
now standard, delay_length, . , .
, , , . i s:
\ \::= procedure \ \ [(\ \)];
\ \: :=[pure | impure] function \ \ |\ \[(\ \)] return \ ;
VHDL . , . . (overloading) . , integer, real, signed, unsigned , .
, :
