VHDL
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- () 10, , 120.
, , , 120.0, 1.202.
- 0 16. :
\ \::=\\#\ \#[\\], , 10#112# = 1#70# = 5#422# = 2#1110000# = 2#111#4.
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- . VHDL - . . , , . , VHDL .
() . :
type \ \ is (\ \
{ \});
-, . ,
type \\ is (\\,\\\);
, \\ , \\ 0, \\ - 2. . :
type \ \ is range \ \;
\ \::=\\ to \\
|\\ downto \\.
. :
-2147483647 to 2147483647.
, . .
. . :
type \ \ is
array (\ \<>) of \ ;
\ integer - integer.
:
type \ \ is
array ( \ of \ );
, , , . ( - ) , , .
VHDL . , :
type MATR is array (integer range <>, integer range <>) of integer
, , . :
type \ \ is record \ :\ ; {\ :\ ;} end ^[\ \];
, . VHDL time, (fs), (ps), (ns) .. , , , . VHDL .
(access) (file). , , . , . - .
. :
\\:: =subtype \ is \ \ [\\];
\\ - , . . . , - , .
VHDL standard, . :
type boolean is (false, true);
type bit is CO', '!');
type integer is range -2147483647 to 2147483647;
subtype natural is integer range 0 to 2147483647;
type bitvector is array (natural range <>) of bit;
character , , , positive, integer, string character.
, - . . :
signal:\\{,\\}[:= \ \];
- \ \ - , , .
, . ( ). :
constant thousand: integer:=1000;
- , , . , . :
\ \::=
[shared] variable \\{\}:\\ [:=\ ;
:
variable byte_int: integer range -128 to 127:=0;
shared. .
VHDL , entity. . . , , , . : in - , out - , inout - , buffer - - link. :
\ \::=port (\ \
{; \ \}); \ \::=\\: in I out|inout|buffer|1ink
\\ [:=\ \].
link . , VHDL .
generi
generic . , , , . , . :
\ \::=
(\6 \
{; \ \}); \ \::=
\\:\\[:=\ \]
- , . loop.
- , . , , - , - .
. . , :
signal bb:bit:=aa; signal aa:bit: = ';
, .
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VHDL . , , , , .
VHDL 3.1 .
and, or, nand, nor, xor, | |
=, /=f <, <=, >, >= | |
sll, srl, sla, sra, rol, ror | |
+, -, & () | |
() | + - |
*, /, mod, rem | |
**, abs, not |
. bit boolean, () bit boolean. , :
(a or b) and and (d or ).
boolean. "=" "/=" . , () .
, (), . , . , . . , "0111" >=01011" true.
integer. , "100110" sra 3 "111100", .. 3 .
- "+", "-" . "&" . - . , "101" & ' & "10" "101110".
. . "*", "/" . mod (), rem () . abs "**" , .
. , , . , "+" numericbit IEEE , . .
, "/". mod, rem , "**" 2, .
, . , . , , , , , , , . .
+,- . . .
, . , vect(4) 4- vect, arr(i,j) (i,j) .
- . :
\-\::=\\(\\ to | downto \\)
\\ - , \\. to downto , . , :
signal A: bitvector(15 downto 0);
(15 downto 8) - .
. :
\ \::=\ \.\ \
\ \ - , , -, . , :
type compvect is record
(Re: bit_vector(0 to 15); Im:bit_vector(0 to 15)); end record; signal A: comp_vect;
A.Re(0 to 7) - Re comp_vect.
. . :
\ \::=\ \ ([\ =>\] \\ {,[\ => ] \\});
\ \ - , , \ - . - , . .
- , . "=>", .
, iEEE.Math_.Real :
function Sin (x: in real) return real;
: SIN(x=>math_2_pI * angle) sin(math_2pi * angle),
math__2_pi - , 2, .
. VHDL , , , . .
: . . , , real integer, integer natural, . , :
C:=integer(123.5);
, .. 124.
, . , boolean bit - .. . , , boolean Y bit , :
if X then Y: = 'l'; else Y: = '0'; end if;
. .
. . - , . , objectl'left objectl . , .
. , , .. . :
\\::=(\ \ { \}) \ \::=[\\ =>] \\ \\::=\ { \}
\\::=\ \|\\|\ \| others
. . . , :
variable v_5: bit_vector (0 to 4): = 09, '0', ,01, '1', ');
0, 1 2 0, 2,3 - 1. , . , v_5:
(3|4 => '1\ others => '0') (0 to 2 => '0'; 3 to 4 => ').
others . , , - , :
9,'9, 3 to 4 => '1\ others -> '').
VHDL.
, , , , (i => '!', others => '0') £- 1, .
\ , :
type complex is record (Re: integer; im: integer); end record; variable x is complex:=(Re => 1000, im => 0);
. . , , . :
\ \::=\ \'(\\)
,
type vect is bitvector(0 to 9); var x: vect;
(3=>'l'.others => '0') . :
x^vect'O^'l'.others -> '0');
, VHDL . , - (elaboration). , . , (generic), , . , , case, , , . . . , . , , .
,
signal n: integer;
signal A: bit_vector(16 downto n+1);
- = -2147483647, , .. +1 - .
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VHDL
, . , .
: and "", not - "" .. . .
"" "". "" " " -, .
, , , , - . positive natural, , integer - .
abs , .
, , , , , . integer, .
"&" , , , .
.
, .
integer , 32- 32- . : , :
variable a, b: integer range (-128 to 127);
a+b 8- .
. , . , . , , . . 24 , a+b+c+d (a+b)+(c+d).
, , -.
VHDL . VHDL . .
. :
\\:= \\; - \\ <= \\; - .
\\ , , var, , var(l), , var(0 to 1), , .var , (ReTim).
. .
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signal d:bit_vector(0 to 7);
d <= (others => '0'); d(l to 3) <= "Oil"; d(4 to 5) <= "II; wait...
d "00111100".
. , , . , -
.
ieee.STD_logic_1164, to , stcLlogic, , .
. :
\ \::=\\ <= [\ \] \\; \6 \::= transport |[reject \ \] inertia! \\::= \\ [after \ \]
{, \\ [after \ \] }
(waveform) , : - . , , .
transport , , , , . \ \, time.
inertia! , . reject , . , after. inertia"!. .
Y<= after 10 ns;
- Y 10 , 10 .
Y<= '0\ '1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
- Y 0, 10 - 1, 20 - 0,
30 - 1.
.
Y<= , + after delay_sum;
- Y , ,
delay_sum - .
Y<= transport X after 1000 ns;
- 1 .
Y<= reject t_rej inertial A and after t_d;
- "" t_d,
t_rej.
wai t
VHDL . , , , . wai t:
\ waitY-:=wait [on \ \ { \}]
[until \6 \] [for \ \];
on , until - , a for - .
wait on clk, rst;
clk RST.
wait until CLK='l';
clk '0' '1', .. .
wait for clk_period;
, clk_period ti me.
. wait -
, .
i f
, , . :
\ if\::=if \ 1\ then
{\ 1\}
[ { elsif \ 2\ then
{\ 2\}]
[else
{"^ 3\}]
end if;
, . , true. if .
case
. :
\ case\::=case \ \ is
when \\ => {"^ \} {when \\ => {"^ \}} end case; \\:= \\{ | \\}
\ \ . \\ , \\ , , 0 to 4. , , , .. . others, . others , -
, \\. case:
variable sel, a: integer 0 to 9;
case sel is
when 0 => a <= 0;
when 112 I 3 => a <= 1;
when 4 to 7 -> a <= 2;
when others => a <= 3;
end case;
null - , . , case - , :
case sel is
when 0 => a <= 0; when 1 to 9 => a <= b; when others => null; end case;
. :
\ \::=[\\:][\ \]1 ■^ \}
{next[\MeTKa\][when \\];} {\\] [when \\];} end loop [\\]; \ \::=while \\
| for \ \ in \\
\\ , , next exit.
, loop end loop , \\ false. , false, .
:
variable vec: bit_vector(l to n); variable or_vec:bit; variable i:natural;
i:=l;
or_vec:='0'; while i<=n loop
or_vec:= or_vec or vec(i);
i: =i +1; end loop;
or_vec, vec . = 0, . :
variable vec: bit_vector(l to n); variable or_vec:bit;
or_vec:='0'; for i in 1 to n loop
or_vec:= or_vec or vec(i); end loop;
i 1,2,... 1 to . : , -1,... : n downto 1. ,