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Function Mor(xl,x2:bit) return boolean is begi n




return (xl or x2) ='l'', end; end package body;

, library use, , , if, when .

use

, , , , .


, , use. :

\ use\::= use \ \ {, \ \ };

\ \::= \1\. \2\

\2\::= \\ | \ \ |

\1\ , , . , . - , , - , , "*". all , , . , std_7ogic_arith IEEE :

use IEEE.std_logic_arith.,,-n, iEEE.std_logic_arith."+";

use IEEE.std_logic_arith.all;

. VHDL , . :

\ ::= alias \\ |

\ | \ \ [:\\] is \\ [\\];

, . ,

alias COP: bit_vector(7 downto 0) is INSTRUCTION(31 downto 24);

instruction , . (7) instruction(31).

j. . ,

alias vect is std_logic_vector;

, vect std_logic_vector, , .


. :

alias to_v is conv_std_logic_vector

[integer, integer return std_logic_vector];

, , , .

, , , :

alias PI is IEEE.math_real.math_pi;

- .

- , . , , .

, , . VHDL . - , , . , .

, . , , . , use, , , .

, , . , , , , .

, , . , , .

,


. , , , . , . , .

- , . , , , . .

. , , - , RG_ACC. . , .

, , , , . :

\ ::=

configuration \\ of \ \ is for \ \

{for : \ ; end for;} end for; end [configuration] [\\];

\ \::=\

{ } | others | all ::= use entity

\ [(^ \)]

(test bench), -, , alu_tb(tb_arch). -


, , ALU (unit under test), , .. , , RTL. , , , :

configuration testbench_for_alu of alu_tb is

for TB_ARCH

for UUT: ALU

use entity work.ALU(RTL); end for; end for;

end TESTBENCH_FOR_ALU;

, , ( ), , ( , - use open).

, , library use, .

-.

VHDL - . . VHDL. . , , . .

, , , wait .


, . , , wait . , :

ADDER_D:A<=B+C;

adder_p:process begin <=+; wait on ,; end process;

:

\ \::= \\<= [\ \]

{\\ when \6 \ else } \\|> \6 \];

.

, , :

cntrl<= one when st=l else

two when st=2 or st=3 else three;

process(st,one,two,three) begin

if st=l then

cntrl<= one; elsif st=2 or st=3 then

cntrl<= two; else

cntrl<=three; end if; end process;

:


\ \::= with \\ select {\\<= [\ \]{\\ when \\,}

\rpa0MK\[when others ];

\\ , case. , , :

With st select

cntrl<= one when 1,

two when 2 to 3, three when others;

, :





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