SDRAM (Synchronous DRAM) . SDRAM : , RAS#, CAS#, WE# ( ) CS# ( ) (. 7.3). , . RAS CAS, FPM.
7.3. SDRAM
| I/O | ||
| CLK | I | Clock Input , |
| CKE | I | Clock Enable ( ). Power Down, Suspend Self Refresh |
| CS# | I | Chip Select ( ). , |
| RAS#, CAS#, WE# | I | Row Address Strobe, Column Address Strobe, Write Enable , ( ) |
| BS0, BS1 BA0, BA1 | I | Bank Selects Bank Address , |
| [0:12] | I | Address . Bank Activate . Read/Write A[0:9] 11 . 10 Read/Write ( 10=1), Precharge A10=1 ( BS0, BS1) |
| DQx | I/O | Data Input/Output |
| DQM | I | Data Mask . ( 2 ). , ( ) |
| VSS, VDD | ||
| VSSQ, VDDQ | . |
WR. . . , CAS Latency (CL), TCAC . . SDRAM . 7.6. WR, RD , ACT. PRE. 2, CL = 3.
. 7.6. SDRAM: R0/C0 R0/C0+1, D , R0/C1 R0/C1 +1
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( CBR ) REF, (idle) .
SDRAM . (burst length=1, 2, 4, 8 ), (wrap mode: interleave/linear /) . (normal), (Multiple Burst with Single Write). WB, WT-.
, , (, burst length=4 ).
( ) . , ( ).
Write DQM. .
SDRAM , CKE.
(Self Refresh) , .
(Power Down Mode) CKE NOP INHBT. . , .
CKE=L, Clock Suspend Mode, ( ) .
SDRAM :
♦ ;
♦ CL (Cas Latency) (2 3);
♦ TRCD RAS-CAS, (2 3);
♦ TRP RAS;
♦ TRC ;
♦ TAC .
SDRAM, PC- , : PC66 ( , ), PC100 PC133 66,6, 100 133 . . 7.4. SDRAM TAC; , , . -10 66 . -8 100 , , , . , , Micron -8-8 100 CL = 3, a -8D -8 CL = 2.
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7.4. SDRAM
| CL | TRCD | TRP | TRC | |||
| PC66 | 3 | 2 | 3 | 8 | ||
| 2 | 2 | 2 | 7 | |||
| PC100 | 3 | 3 | 3 | 8 | ||
| 3 | 2 | 2 | 7 | |||
| 2 | 2 | 2 | 7 | |||
| PC133 | 3 | 3 | 3 | 9 | ||
| 3 | 2 | 2 | 8 | |||
| 2 | 3 | 2 | 8 | |||
| 2 | 2 | 2 | 8 |
, . SDRAM, , , , .
100 100 / 1 . SDRAM DIMM 8- , 800 /. 133 1064 /. , . - , , . , SDRAM, . , , , FPM EDO DRAM.
DDR SDRAM SDRAM. (Dual Data Rate ), DDR SDRAM (. 7.7). 100 DDR SDRAM 200 / , 8- DIMM 1600 /. (100 ) . .
♦ CLK CLK# (Differential clock inputs). .
♦ DQS. : DQS , (). , DQS. DQM.
♦ DQS (CLK) DLL (Delay Locked Loop) DQS CLK. ( DQS CLK) .
. 7.7. ́ DDR SDRAM: a , CL = 2, 4; , 4, D1
DDR SDRAM DLL; . DLL ( ). DLL DQS CLK, , , .
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SDRAM, , DDR SDRAM ( DQM) (write latency). CAS Latency (CL = 2, 2,5, 3).
DDR-II SDRAM, .
SDRAM . , . CL (CAS Latency) , , , CL, , TCAC. DDR SDRAM CL, . DDR SDRAM - DLL .
SDRAM SIMM; DIMM ( ) . DDR SDRAM SDRAM. . SDRAM 90- , DDR SDRAM .
Rambus DRAM
RDRAM (Rambus DRAM) , . - , . () RDRAM , . DDR SDRAM, RDRAM . RDRAM (16 ) , , , . .
64- 8 , 256- 32 . , . ( ) , ( ). 16 128 144 ( ) . 1/8 , RAS CAS. RDRAM 4053 .
RDRAM (Rambus Channel) - . , , , . . 400 , . , 800 /. 30 RSL (Rambus System Logic) 4 , . . 7.8. 32 , . , DEVID. (Device Enumeration) , -. SCK, CMD, SIO.
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. 7.8. Direct RDRAM
(Clock To Master). , ( ). , CFM (Clock From Master) , . , . DLL (Delay Locked Loop) DQS CLK.
. RSL : 0 VTERM = 1,8 , . 1 1,0 . N-ϻ . , ( ). VREF = 1,4 VTERM. , CTMN CFM, CFMN . , .
: 3- ROW[2:0], 5- COL[4:0] (2×9 ) DQA[8:0] DQB[8:0]. ( RDRAM) . , 4 (8 ) (10 ). 8 ; 24 , 40 16 8 9 .
( ) ( BEDO SDRAM) . .
. 7.9, SDRAM , (SDRAM) . ROW , . : ROWA COLC, TCAC. , . , , , . , COLC. , , . .
. 7.9. RDRAM
(. 7.10) . DRAM SDRAM, , RDRAM COLC TCWD ( ). COLC ( ). ( SDRAM CAS Latency 23 10 ). , . , 15 . .
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. 7.10. RDRAM
RDRAM , , . ( D) , - (sens amp) (retire) . , ( ). TRTR , TRCD, .
RDRAM . ROW COL , . , SDRAM.
, ; .
RDRAM . , 100- 250- . RDRAM ( 100 ) ; . .
SCK, CMD SIO (PDN NAP). .
, , , . , . . .
, . , SIO0 SIO1 . CMD , SIO . (SDEVID) , . , ( ) . SIO, .
, DLL. . (DEVID), SDEVID ( ).
RDRAM . , , , . , , . RDRAM Rambus. RDRAM P6 (, 1820, 1840), Pentium 4 (1850 32- , RIMM) .
RDRAM RIMM, . RIMM ( 64, 96, 128 256 ). Intel . - Continuity module. RIMM, , , Rambus. , RIMM. , (. ).
