PC, , -, , , , . , .
DRAM (Dynamic RAM) , , . , ( ) . , ( ).
DRAM . MA (Multiplexed Address) RAS# (Row Access Strobe) CAS# (Column Access Strobe). . 7.1.
7.1.
RAS# | Row Access Strobe . ; . ( ) , RAS (TRP RAS precharge time) |
CAS# | Column Access Strobe . ; (TCAS) . ( ) , CAS (TCP CAS precharge time) |
MAi | Multiplexed Address . RAS# , CAS# . . 4 11 11 12×10 |
WE# | Write Enable . CAS# WE# (Early Write , ), WE# CAS# (Delayed Write ). WE# CAS# , EDO DRAM |
# | Output Enable . |
DB-In | Data Bit Input ( ) |
DB-Out | Data Bit Output ( ). RAS#, CAS#, OE# WE#; . EDO CAS#. |
DQx | Data Bit ( ) |
N.C. | No Connection |
, ( ) RAS# CAS# ( ). WE# CAS#. . 7.1. , ( RAS#) , TRAC, .
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. 7.1.
DRAM , , CMOS Setup.
♦ TRAC (RAS Access Time) RAS (. ). , , (-7 -70 70 ). 40-100 .
♦ (cycle time) (TWC TRC ). 75-125 .
♦ ( CAS#) TPC (Page CAS Time . . 7.1.1).
♦ RAS# CAS# TRAS TCAS ( ) (. ).
♦ RAS CAS TRP, TCP (RAS CAS Precharge Time) .
♦ RAS# CAS# TRCD (RAS to CAS Delay).
♦ CAS# (TCAC).
. . 7.2 , . CMOS Setup, , .
7.2. DRAM
TRC, | TRAC, | TPC, | TCAS, | TCP, | |
-4 | 75 | 40 | 15 | 6 | 6 |
-5 | 100 | 50 | 20 | 8 | 8 |
-6 | 104 | 60 | 25 | 10 | 10 |
-7 | 110 | 70 | 30 | 12 | 12 |
, , SDRAM, DDR SDRAM Rambus DRAM , .
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( ) , (Memory Refresh ) ( ) . , CAS#, ROR (RAS Only Refresh RAS#). CBR (CAS Before RAS), . RAS# CAS# ( ). COR , CBR . (hidden refresh) CBR.
CBR Auto Refresh. Self Refresh Sleep Mode .