:
, :
9. 8 32 .
10. 53713 (1 4 .)
11. 1533
12. /
13. 
, MR, MW,CLK,MAD
14. :
: 2 ,
: tcy
15. 2
VHDL- .
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity full_zu is
Port (MS: in STD_LOGIC;
MR: in STD_LOGIC;
MW: in STD_LOGIC;
MAD: inout STD_LOGIC_VECTOR (31 downto 0);
CLK: in STD_LOGIC);
end full_zu;
architecture Behavioral of full_zu is
--
component control_unit is
port(CLK,MS,MR,MW:in std_logic; c1,c2,c3,c4,c5,c6:out std_logic);
end component;
--
component memory_matrix is
Port (ADR: in STD_LOGIC_VECTOR (9 downto 0);
CS1: in STD_LOGIC;
CS2: in STD_LOGIC;
CS3: in STD_LOGIC;
CS4: in STD_LOGIC;
CS5: in STD_LOGIC;
CS6: in STD_LOGIC;
CS7: in STD_LOGIC;
CS8: in STD_LOGIC;
WRRD: in STD_LOGIC;
DIOUT: inout STD_LOGIC_VECTOR (31 downto 0));
end component;
-- RGI,RGO,RGA
component KP1533IR22_V is
GENERIC (Tplh:time:=12 ns;
Tphl:time:=16 ns;
Tpzh:time:=40 ns;
Tpzl:time:=30 ns);
PORT (D: IN STD_LOGIC_VECTOR(0 TO 7);
EZ,C: IN std_logic;
Q: OUT STD_LOGIC_VECTOR(0 TO 7));
end component;
--
component KP1533ID7_V is
GENERIC (Tpd:time:=20 ns;
Tpe:time:=17 ns);
PORT (D: IN STD_LOGIC_VECTOR(0 TO 2);
C: IN STD_LOGIC_VECTOR(0 TO 2);
Y: OUT STD_LOGIC_VECTOR(0 TO 7));
end component;
--
signal log0:std_logic:='0';
signal log1:std_logic:='1';
signal C1,C2,C3,C4,C5,C6:std_logic;
signal CSR1,CSR2,CSR3,CSR4,CSR5,CSR6,CSR7,CSR8:std_logic:='1';
signal AtoM:std_logic_vector(9 downto 0); --10 RGA
signal Row:std_logic_vector(0 to 2); --3
signal emptyvector:std_logic_vector(0 to 2);
signal MEMinout:std_logic_vector(31 downto 0);
begin
CU: control_unit port map (CLK =>CLK, MS =>MS, MR=> MR, MW=>MW, c1=>C1,c2=>C2,c3=>C3,c4=>C4,c5=>C5,c6=>C6);
MM: memory_matrix port map (ADR=>AtoM,CS1=>CSR1,CS2=>CSR2,CS3=>CSR3,CS4=>CSR4,CS5=>CSR5,CS6=>CSR6,CS7=>CSR7,CS8=>CSR8,WRRD=>C3,DIOUT=>MEMinout(31 downto 0));
RGAh: KP1533IR22_V port map (D=>MAD(12 downto 5),EZ=>log0,C=>C1,Q=>AtoM(9 downto 2));
RGAl: KP1533IR22_V port map (D(0 to 4)=>MAD(4 downto 0),D(5)=>log0,D(6)=>log0,D(7)=>log0,EZ=>log0,C=>C1,Q(0 to 1)=>AtoM(1 downto 0),Q(2 to 4)=>Row,Q(5 to 7)=>emptyvector);
DCA: KP1533ID7_V port map(D=>Row,C(0)=>C2,C(1)=>log0,C(2)=>log0,Y(0)=>CSR1,Y(1)=>CSR2,Y(2)=>CSR3,Y(3)=>CSR4,Y(4)=>CSR5,Y(5)=>CSR6,Y(6)=>CSR7,Y(7)=>CSR8);
|
|
|
RGI1: KP1533IR22_V port map(D=>MAD(31 downto 24), EZ=>log0, C=>C4, Q=>MEMinout(31 downto 24));
RGI2: KP1533IR22_V port map(D=>MAD(23 downto 16), EZ=>log0, C=>C4, Q=>MEMinout(23 downto 16));
RGI3: KP1533IR22_V port map(D=>MAD(15 downto 8), EZ=>log0, C=>C4, Q=>MEMinout(15 downto 8));
RGI4: KP1533IR22_V port map(D=>MAD(7 downto 0), EZ=>log0, C=>C4, Q=>MEMinout(7 downto 0));
RGO1: KP1533IR22_V port map(D=>MEMinout(31 downto 24), EZ=>C6, C=>C5, Q=>MAD(31 downto 24));
RGO2: KP1533IR22_V port map(D=>MEMinout(23 downto 16), EZ=>C6, C=>C5, Q=>MAD(23 downto 16));
RGO3: KP1533IR22_V port map(D=>MEMinout(15 downto 8), EZ=>C6, C=>C5, Q=>MAD(15 downto 8));
RGO4: KP1533IR22_V port map(D=>MEMinout(7 downto 0), EZ=>C6, C=>C5, Q=>MAD(7 downto 0));
end Behavioral;
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1. .. VHDL VERILOG . ─ .: , 2012. ─ 220 .
2. .. VHDL VERILOG . ─ .: -, 2003. ─ 320
3. .. . XILINX.
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