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1. ( - 1533,1554 F74) (15). , 1533, KP1533_ID14 2-4 6 8 , 15
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1
- 155423. .
1554- 1554 work. . 1554, use work.KP1554. KP1554IR23; , . , .
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.KP1554.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity reg is
Port (d00: in STD_LOGIC;
d10: in STD_LOGIC;
d20: in STD_LOGIC;
d30: in STD_LOGIC;
d40: in STD_LOGIC;
d50: in STD_LOGIC;
d60: in STD_LOGIC;
d70: in STD_LOGIC;
ez0: in STD_LOGIC;
clk0: in STD_LOGIC;
q00: out STD_LOGIC;
q10: out STD_LOGIC;
q20: out STD_LOGIC;
q30: out STD_LOGIC;
q40: out STD_LOGIC;
q50: out STD_LOGIC;
q60: out STD_LOGIC;
q70: out STD_LOGIC);
end reg;
architecture Behavioral of reg is
begin
reg1: KP1554IR23 port map (
d00,d10,d20,d30,d40,d50,d60,d70,ez0,clk0,q00,q10,q20,q30,q40,q50,q60,q70);
end Behavioral;
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY test_vhd IS
END test_vhd;
ARCHITECTURE behavior OF test_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT reg
PORT(
d00: IN std_logic;
d10: IN std_logic;
d20: IN std_logic;
d30: IN std_logic;
d40: IN std_logic;
d50: IN std_logic;
d60: IN std_logic;
d70: IN std_logic;
clk0: IN std_logic;
ez0: IN std_logic;
q00: OUT std_logic;
q10: OUT std_logic;
q20: OUT std_logic;
q30: OUT std_logic;
q40: OUT std_logic;
q50: OUT std_logic;
q60: OUT std_logic;
|
|
|
q70: OUT std_logic
);
END COMPONENT;
--Inputs
SIGNAL d00: std_logic:= '0';
SIGNAL d10: std_logic:= '0';
SIGNAL d20: std_logic:= '0';
SIGNAL d30: std_logic:= '0';
SIGNAL d40: std_logic:= '0';
SIGNAL d50: std_logic:= '0';
SIGNAL d60: std_logic:= '0';
SIGNAL d70: std_logic:= '0';
SIGNAL clk0: std_logic:= '0';
SIGNAL ez0: std_logic:= '0';
--Outputs
SIGNAL q00: std_logic;
SIGNAL q10: std_logic;
SIGNAL q20: std_logic;
SIGNAL q30: std_logic;
SIGNAL q40: std_logic;
SIGNAL q50: std_logic;
SIGNAL q60: std_logic;
SIGNAL q70: std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: reg PORT MAP(
d00 => d00,
d10 => d10,
d20 => d20,
d30 => d30,
d40 => d40,
d50 => d50,
d60 => d60,
d70 => d70,
ez0 => ez0,
clk0 => clk0,
q00 => q00,
q10 => q10,
q20 => q20,
q30 => q30,
q40 => q40,
q50 => q50,
q60 => q60,
q70 => q70
);
gen: process --- - 20 ns
begin
clk0<=not clk0; wait for 25 ns;
end process;
tb: PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 110 ns;
d00<='1';
d10<='1';
d20<='1';
d30<='1';
d40<='0';
d50<='0';
d60<='0';
d70<='0';
wait for 50 ns;
d00<='0';
d10<='0';
d20<='1';
d30<='1';
d40<='1';
d50<='1';
d60<='0';
d70<='0';
wait for 5 ns;-- ?
ez0<='1';--
wait for 50 ns;
wait; -- will wait forever
END PROCESS;
END;
2
. , : 155423 155414:
, VHDL, , .
(Lab1_2_CT.vhd):
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity Lab1_2_CT is
Port (C0: in STD_LOGIC;
C1: in STD_LOGIC;
R: in STD_LOGIC;
D: out UNSIGNED (3 downto 0):=(others => '0'));
end Lab1_2_CT;
architecture CT of Lab1_2_CT is
signal Dtmp: UNSIGNED (3 downto 0):=(others => '0');
begin
process(C0,C1,R) begin
if ((rising_edge(C0) and C1 = '1') or (falling_edge(C1) and C0 = '0')) and R='1' then
if Dtmp = 15 then
Dtmp <= (others =>'0') after 20 ns;
else
Dtmp <= Dtmp+1 after 20 ns;
end if;
end if;
if falling_edge (R) then
Dtmp <= (others =>'0') after 20 ns;
end if;
end process;
D <= Dtmp;
end CT;
(Lab1_2_DC.vhd):
----------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity Lab1_2_DC is
Port (A0: in STD_LOGIC;
A1: in STD_LOGIC;
E: in STD_LOGIC;
DO: out UNSIGNED (3 downto 0):=(others => '1'));
end Lab1_2_DC;
architecture DC of Lab1_2_DC is
begin
process (A0,A1,E) begin
if E = '1' then
DO <= "1111" after 10 ns;
else
if A1 = '0' then
if A0 = '0' then
DO <= "1110" after 10 ns;
else
DO <= "1101" after 10 ns;
end if;
else
if A0 = '0' then
DO <= "1011" after 10 ns;
else
DO <= "0111" after 10 ns;
end if;
end if;
end if;
end process;
end DC;
- (Lab1_2_CTDC.vhd):
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity Lab1_2_CTDC is
Port (C0: in STD_LOGIC;
C1: in STD_LOGIC;
R: in STD_LOGIC;
DO: out UNSIGNED (3 downto 0));
end Lab1_2_CTDC;
architecture CTDC of Lab1_2_CTDC is
component Lab1_2_CT Port(C0: in STD_LOGIC;
|
|
|
C1: in STD_LOGIC;
R: in STD_LOGIC;
D: out UNSIGNED (3 downto 0));
end component;
component Lab1_2_DC Port(A0: in STD_LOGIC;
A1: in STD_LOGIC;
E: in STD_LOGIC;
DO: out UNSIGNED (3 downto 0));
end component;
signal S: UNSIGNED (3 downto 0);
begin
S1: Lab1_2_CT port map (C0, C1, R, S);
S2: Lab1_2_DC port map (S(0), S(1), S(2), DO);
end CTDC;
(Lab1_2_CT_TB.vhd):
--------------------------------------------------------------------------------
--
-- VHDL Test Bench Created by ISE for module: Lab1_2_CT
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the
--post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
ENTITY Lab1_2_CT_TB IS
END Lab1_2_CT_TB;
ARCHITECTURE behavior OF Lab1_2_CT_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Lab1_2_CT
PORT(
C0: IN std_logic;
C1: IN std_logic;
R: IN std_logic;
D: OUT UNSIGNED (3 downto 0)
);
END COMPONENT;
--Inputs
signal C0: std_logic:= '0';
signal C1: std_logic:= '1';
signal R: std_logic:= '1';
--Outputs
signal D: UNSIGNED(3 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant C_period: time:= 50 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Lab1_2_CT PORT MAP (
C0 => C0,
C1 => C1,
R => R,
D => D
);
-- Clock process definitions
C_process:process
begin
C0 <= '0';
wait for C_period/2;
C0 <= '1';
wait for C_period/2;
end process;
stim_proc: process
begin
-- hold reset state for 1000 ns.
wait for 1000 ns;
R <= '0';
wait for C_period*3;
R <= '1';
end process;
END;
(Lab1_2_DC_TB.vhd):
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Lab1_2_DC_TB IS
END Lab1_2_DC_TB;
ARCHITECTURE behavior OF Lab1_2_DC_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Lab1_2_DC
PORT(
A0: IN std_logic;
A1: IN std_logic;
E: IN std_logic;
DO: OUT UNSIGNED(3 downto 0)
);
END COMPONENT;
--Inputs
signal A0: std_logic:= '0';
signal A1: std_logic:= '0';
signal E: std_logic:= '0';
--Outputs
signal DO: UNSIGNED(3 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant C_period: time:= 50 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Lab1_2_DC PORT MAP (
A0 => A0,
A1 => A1,
E => E,
DO => DO
);
-- Stimulus process
stim_proc: process
begin
wait for 150 ns;
A0 <= '1';
wait for C_period;
A0 <= '0';
A1 <= '1';
wait for C_period;
A0 <= '1';
wait for 3*C_period;
E <= '1';
wait for 3*C_period;
end process;
END;
(Lab1_2_CTDC_TB.vhd):
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Lab1_2_CTDC_TB IS
END Lab1_2_CTDC_TB;
ARCHITECTURE behavior OF Lab1_2_CTDC_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Lab1_2_CTDC
PORT(
C0: IN std_logic;
C1: IN std_logic;
R: IN std_logic;
DO: out UNSIGNED (3 downto 0)
);
END COMPONENT;
--Inputs
signal C0: std_logic:= '0';
signal C1: std_logic:= '1';
signal R: std_logic:= '1';
--Outputs
signal DO: UNSIGNED (3 downto 0);
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
constant C_period: time:= 50 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Lab1_2_CTDC PORT MAP (
C0 => C0,
C1 => C1,
R => R,
DO => DO
);
-- Clock process definitions
C0_process:process
begin
C0 <= '0';
wait for C_period/2;
C0 <= '1';
wait for C_period/2;
end process;
stim_proc: process
begin
wait for 1000 ns;
R <= '0';
wait for C_period*3;
R <= '1';
end process;
END;
-------------------------------------------------------------------------------------------------
Lab1_2_CT
Lab1_2_CT
Lab1_2_CTDC
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----------------------------------------------------------------------------------
-- Company:
-- Engineer: POLIAKOV-AGAFONOV
-- Create Date: 02:23:34 10/26/2007
-- Design Name:
-- Module Name: CNT - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.KP15xx.all;
entity CNT is
Port (clk: in STD_LOGIC;
ECR: in STD_LOGIC;
ECT: in STD_LOGIC;
nEWR: in STD_LOGIC;
nR: in STD_LOGIC;
q1: out STD_LOGIC_VECTOR (0 to 7);
q2: out STD_LOGIC_VECTOR (0 to 7);
q1_v: out STD_LOGIC_VECTOR (0 to 7);
q2_v: out STD_LOGIC_VECTOR (0 to 7)
);
end CNT;
architecture Behavioral of CNT is
SIGNAL wire_CR1: STD_LOGIC;
SIGNAL wire_CR2: STD_LOGIC;
SIGNAL wire_CR1_v: STD_LOGIC;
SIGNAL wire_CR2_v: STD_LOGIC;
begin
--
DD1: IE10 PORT MAP (D1=>'0', D2=>'1', D4=>'0', D8=>'0', ECT=>ECT, ECR=>ECR, C=>clk, EWR=>nEWR, R=>nR,
Q1=>q1(0), Q2=>q1(1), Q4=>q1(2), Q8=>q1(3), CR=>wire_CR1);
DD2: IE9 PORT MAP (D1=>'0', D2=>'1', D4=>'0', D8=>'0', ECT=>wire_CR1, ECR=>wire_CR1, C=>clk, EWR=>nEWR, R=>nR,
Q1=>q1(4), Q2=>q1(5), Q4=>q1(6), Q8=>q1(7));
DD3: IE18 PORT MAP (D1=>'0', D2=>'1', D4=>'0', D8=>'0', ECT=>ECT, ECR=>ECR, C=>clk, EWR=>nEWR, R=>nR,
Q1=>q2(0), Q2=>q2(1), Q4=>q2(2), Q8=>q2(3), CR=>wire_CR2);
DD4: IE11 PORT MAP (D1=>'0', D2=>'1', D4=>'0', D8=>'0', ECT=>wire_CR2, ECR=>wire_CR2, C=>clk, EWR=>nEWR, R=>nR,
Q1=>q2(4), Q2=>q2(5), Q4=>q2(6), Q8=>q2(7));
---------------------------------------------------------
DD1_V: IE10_V PORT MAP (D=>"0100",--D1=>'0', D2=>'1', D4=>'0', D8=>'0',
ECT=>ECT, ECR=>ECR, C=>clk, EWR=>nEWR, R=>nR,
Q=>q1_v(0 to 3), --Q1=>q1(0), Q2=>q1(1), Q4=>q1(2), Q8=>q1(3),
CR=>wire_CR1_v
);
DD2_V: IE9_V
PORT MAP (D=>"0100", --D1=>'0', D2=>'1', D4=>'0', D8=>'0',
ECT=>wire_CR1, ECR=>wire_CR1_v, C=>clk, EWR=>nEWR, R=>nR,
Q=>q1_v(4 to 7) --Q1=>q1(4), Q2=>q1(5), Q4=>q1(6), Q8=>q1(7)
);
DD3_V: IE18_V
PORT MAP (D=>"0100",--D1=>'0', D2=>'1', D4=>'0', D8=>'0',
ECT=>ECT, ECR=>ECR, C=>clk, EWR=>nEWR, R=>nR,
Q=>q2_v(0 to 3),--Q1=>q2(0), Q2=>q2(1), Q4=>q2(2), Q8=>q2(3),
CR=>wire_CR2_v
);
DD4_V: IE11_V
PORT MAP (D=>"0100",--D1=>'0', D2=>'1', D4=>'0', D8=>'0',
ECT=>wire_CR2_v, ECR=>wire_CR2_v, C=>clk, EWR=>nEWR, R=>nR,
Q=>q2_v(4 to 7) --Q1=>q2(4), Q2=>q2(5), Q4=>q2(6), Q8=>q2(7)
);
end Behavioral;
