1. 8K x 36
2. , 53713,
14; tA(A) ≤ 200
3. 1554
4.
5. MS,MR/MW
6. , 2
MS Tcy
7. 2
8. -10 +50
, 3-
, 3- 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity CU is
Port (CLK: in STD_LOGIC;
Ucc: in STD_LOGIC;
MSm: in STD_LOGIC;
AEN: in STD_LOGIC;
MR_MW: in STD_LOGIC;
EVR: in STD_LOGIC;
CA: inout STD_LOGIC;
OE: out STD_LOGIC;
nCS: inout STD_LOGIC;
COB: inout STD_LOGIC;
CBA: inout STD_LOGIC;
EER: out STD_LOGIC;
nRW: inout STD_LOGIC);
end CU;
architecture Behavioral of CU is
component l2CT port(
C00: in STD_LOGIC;
nC01: in STD_LOGIC;
nR0: in STD_LOGIC;
Q: inout UNSIGNED (3 downto 0));
end component;
component l2DC port (
A: in STD_LOGIC_VECTOR (1 downto 0);
nE0: in STD_LOGIC;
Ddc: out STD_LOGIC_VECTOR (3 downto 0));
end component;
component Invert_LN1 port (
nin: in STD_LOGIC;
nout: out STD_LOGIC);
end component;
component l2_LI1 port (
i1in: in STD_LOGIC;
i2in: in STD_LOGIC;
nout: out STD_LOGIC);
end component;
component ILI2_LL1 port (
i1in: in STD_LOGIC;
i2in: in STD_LOGIC;
nout: out STD_LOGIC);
end component;
component ILI2N_LE1 port (
i1in: in STD_LOGIC;
i2in: in STD_LOGIC;
nout: out STD_LOGIC);
end component;
component Trig_TM2 port (
nR: in STD_LOGIC;
D: in STD_LOGIC;
C: in STD_LOGIC;
neS: in STD_LOGIC;
Q: inout STD_LOGIC;
nQ: inout STD_LOGIC);
end component;
signal Qf: UNSIGNED (3 downto 0);
signal D1:STD_LOGIC_VECTOR (3 downto 0);
signal D2:STD_LOGIC_VECTOR (3 downto 0);
signal nQf2: STD_LOGIC; --
signal nQf3: STD_LOGIC;
signal MSm1: STD_LOGIC; -- 2
signal CLK1: STD_LOGIC; -- 2
signal AEN1: STD_LOGIC; -- AEN
signal TRnQ1: STD_LOGIC; --
signal TRnQ2: STD_LOGIC;
signal TRnQ3: STD_LOGIC;
signal TRnQ4: STD_LOGIC;
signal nMR_MW: STD_LOGIC; -- MR_MW
signal nEVR: STD_LOGIC; -- MR_MW
signal TRQ1: STD_LOGIC; -- q
signal nD12: STD_LOGIC; ---- 2 1
signal nD13: STD_LOGIC; ---- 3 1
signal D12: STD_LOGIC; ----
signal D22: STD_LOGIC; ----
signal D13: STD_LOGIC; ----
signal pust1: STD_LOGIC; ----
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begin
E1: l2_LI1 port map (MSm,nQf3,MSm1);
E2: l2_LI1 port map (CLK,MSm1,CLK1);
E3: Invert_LN1 port map (AEN,AEN1);
E4: l2CT port map (CLK1,Ucc,MSm1,Qf);
E5: l2DC port map (STD_LOGIC_VECTOR(Qf(1 downto 0)),STD_LOGIC(Qf(2)),D1);
E6: Invert_LN1 port map (STD_LOGIC(Qf(2)),nQf2);
E7: l2DC port map (STD_LOGIC_VECTOR(Qf(1 downto 0)),nQf2,D2);
E8: Invert_LN1 port map (STD_LOGIC(Qf(3)),nQf3);
E9: Trig_TM2 port map (nQf3,TRnQ2,AEN1,Ucc,CA,TRnQ2);
E10: Invert_LN1 port map (MR_MW,nMR_MW);
E11: Invert_LN1 port map (EVR,nEVR);
E12: Trig_TM2 port map (nQf3,nRW,nMR_MW,Ucc,TRQ1,nRW);
E13: Invert_LN1 port map (D1(2),nD12);
E14: Invert_LN1 port map (D1(3),nD13);
E15: ILI2N_LE1 port map (D1(2),TRQ1,D12);
E16: ILI2N_LE1 port map (D2(2),nEVR,EER);
E17: l2_LI1 port map (nD12,TRQ1,OE);
E18: l2_LI1 port map (nD13,TRQ1,D22);
E19: ILI2_LL1 port map (D12,D22,D13);
E20: Trig_TM2 port map (nQf3,TRnQ4,D22,Ucc,COB,TRnQ4);
E21: Trig_TM2 port map (D2(3),nCS,D13,Ucc,pust1,nCS);
E22: Trig_TM2 port map (nQf3,Ucc,nD12,Ucc,pust1,CBA);
end Behavioral;
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