(L) () - . CPU , .. .
:
L
L STW ACCU 1
LAR1 AR2 1 (AR1) AR2
LAR1 <D> 1 (32 - )
LAR1 1 ACCU 1
LAR2 <D> (32 - )
LAR2 2 ACCU 1
T
T STW ACCU 1
TAR1 AR2 1 2
TAR1 <D> 1 (32- )
TAR2 <D> 2 (32- )
TAR1 1 ACCU 1
TAR2 1 ACCU 1
CAR 1 2
9
1 2. 1 2. , 1, 2 . CPU , 3 2, 4 3.
4 . , (16 32 ):
+I ACCU 1 ACCU 2 Integer (16-)
-I ACCU 1 ACCU 2 Integer (16-)
*I ACCU 1 ACCU 2 Integer (16-)
/I ACCU 2 ACCU 1 Integer (16-)
+ Integer (16, 32 )
+D ACCU 1 ACCU 2 Double Integer (32-)
-D ACCU 1 ACCU 2 Double Integer (32-)
*D ACCU 1 ACCU 2 Double Integer (32-)
/D ACCU 2 ACCU 1 Double Integer (32-)
MOD Double Integer (32-)
.
10 -