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An integrated circuit is comprised of a single silicon chip containing transistors, diodes, resistors and capacitors, suitably connected to form a complete circuit. The first successful attempt to produce an integrated circuit, in 1959, made use of mesa construction, but this method is known to be quickly replaced by the use of planar techniques.
The important feature of the planar process is the deposition of a silicon dioxide layer on the top surface of the epitaxial wafer which acts as a mask against diffusion. The process involves exposing the wafer to an oxygen atmosphere at high temperature.
After the oxidation process it is necessary to etch holes in the oxide, through which diffusion can take place. The process used is similar to that employed in the manufacture of printed circuit boards. Initially the oxidized surface is coated with a thin film of photo-sensitive emulsion (photoresist). A mask is manufactured, the pattern of which defines the area to be etched, it being opaque (непрозрачный) where etching is to be performed and transparent where the oxide is to be retained. The mask is brought into contact with the wafer and exposed to ultraviolet light. The photoresist under the transparent area of the mask being subjected to the light becomes polymerized and is not affected by the trichlorethylene developer which is subsequently used to dissolve the unexposed resist. When fixed, by baking (отжиг), the remaining photoresist protects the oxide from the window where diffusion is required and, after the surface has been cleaned, the chip is ready for the first diffusion process.
For а р-type diffusion the most generally used dopant proves to be boron. This is deposited on the wafer at high temperature, and diffuses through the window into the silicon. А p-type region is thus created. The oxidization treatment is now repeated and, in this high-temperature process, the open window is sealed with an oxide layer and the base dopant is driven deeper into the silicon. A new mask is used in a second photoresist and etching stage, which opens a window for the diffusion of the emitter region.
For n -type diffusion the most generally used dopants are phosphorus and arsenic. The cycle is supposed to be repeated yet a third time. The emitter window is sealed by oxidization, the emitter dopant is driven in, and new windows are etched in the oxide layer to define the contact areas. Finally the contacts are made by the evaporation of aluminum.
In practice many devices are manufactured at the same time on a single sheet of silicon. These are separated by scribing with a diamond stylus and breaking into individual chips. They are then mounted in suitable packages which allow electrical connections to be readily made and power, dissipated as heat, to escape.
It is necessary to be able to electrically isolate individual devices from each other. This is done by surrounding each component with material of opposite polarity and reverse biasing the semiconductor junction so formed.
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High Pressure Oxidation of Silicon
Silicon oxidation has been a fundamental process of silicon device technology for a long time. However, an understanding of oxidation methods and the phenomena involved is far from complete. An oxidation method that has received increased attention over the last few years is a high pressure oxidation method. This method is known to offer a practical means for thermally growing silicon oxides at lower temperatures and faster rates than those grown in conventional wet (влажный) oxidation. Presently, efforts to implement low temperature processes have become a significant driving force in the evolution of silicon device fabrication technology. The lower temperature aspect of high pressure oxidation has its greatest potential impact in the high density world of submicron VLSI where improvements in process control precision will have a significant effect on performance and yield.
Thin oxide film grown at low temperature by high pressure oxidation has excellent dielectric breakdown strength.
Developments in high pressure oxidation will become more important with progress in other low temperature processes such as ion implantation, laser annealing, and plasma enhanced technology during the next few years.
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Optical lithography has indisputably been the leading integrated circuit pattern defining technique for many years. It is essentially two steps. First, the design and fabrication of the optical mask, which is both costly and time consuming, and secondly, the exposure of the wafer, covered with a layer of light sensitive photoresist, to ultraviolet light shone through the mask. The method is ideal for large scale production because once the expensive mask-making process has been carried out, an unlimited number of wafers may be patterned at very low cost to the producer. On the other hand, where specific or semicustom (полузаказные) ICs are concerned this process has proved unacceptable since the cost and time involved in mask fabrication cannot be justified by the production of only a few devices which may require several iterations for optimum results. For these reasons, electron beam direct-write lithography is proving invaluable in the field of application specific or semicustom integrated circuits. This technique allows fast turnaround, a high flexibility and comparatively low cost for very small batches. In addition, the short wavelength of electron-beam offers very high resolution patterning and so may be essential where sub-micron features are required. Despite the possibility of low throughput, e-beam generated patterns allow either simple wafer-scale integration or devices for several customers, each possibly with a variety of trial designs to be implemented on a single wafer. The major advantage of the e-beam's high resolution capability will be nullified if the resist pattern cannot be very precisely reproduced onto the metallization layer. For this reason wet-etching of the metal with its inherent undercutting is particularly unsuitable and plasma-processing becomes necessary. Reactive ion etching is a type of plasma etching where the wafer is placed on an electrode which is capacitively coupled to an RF generator. A second electrode larger than this driven one is grounded and a plasma is generated by electronic excitation of a low pressure gas contained between them. The arrangement of the system is such that the driven electrode experiences a negative bias with respect to the plasma causing positive ions to be accelerated towards the wafer. This means that not only is there chemical reaction causing removal of the metallization but also ion-enhanced chemical etching and physical sputtering to the vertical etching essential for precise replication of the resist pattern. Dry processing has the added benefits of easily handled process materials, easy automation and good reproducibility.
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Molecular electronics is a new concept of electronic systems. Basically it seeks to integrate into a solid block of the material the functions performed by electronic circuits or even whole systems. Its goal is to rearrange the internal physical properties of the solid in such a way that phenomena occurring within or between domains of molecules will perform a function ordinarily achieved through the use of an assembly of electronic components.
Molecular electronics is the most forward-looking of several modern approaches to the development of small, reliable, efficient electronic systems. Almost all attempt to perform the required electronic functions in solid semiconductor-type materials. Molecular electronics, however, is unique in its goal of doing away with the traditional concept of circuit components. Should this goal be fully realized, or even partially so, it would extend the capabilities of electronic systems well beyond that which can be achieved today. In addition to lowering size and weight, increasing reliability and reducing power requirements, molecular blocks could make possible the execution of tasks now too complex to be performed economically by conventional methods and permit the performance of electronic functions which cannot be achieved at all with lumped (отдельный) components.
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Dry Process Technology
LSI Technology has been the cutting edge of the innovate semiconductor industry. In the field of the process technology, much effort has been made to improve microfabrication and thinner-film formation technology. In particular, improvements in photolithographic and etching techniques are the keys to the integration of more devices on smaller chips, increases in circuit performance, and improvement in wafer process yield.
Dry etching technology represents a new and exciting method for defining precise images in insulators, semiconductors, and metals. Gas plasma etching technology in dry process like RF sputtering, ion beam milling, reactive ion etching, and reactive ion beam etching is widely used as a fundamental tool for the fabrication of MOS, bipolar LSIs, discrete devices and hard mask. It results in improved image size, simplification of the manufacturing process, precise shape control of fine patterns, and development of a cleaner manufacturing process, compared with conventional wet chemical etching processes.
Recently, MOS LSI has sriifted from LSI phase to VLSI phase, which requires a precise pattern less than 3 µm. This transition can be achieved by progress in wafer process technology, including microfabrication as well as device and circuits design technologies. Conventional plasma etching is not adequate in VLSI regions for the delineation of precise patterns because of its inherent undercutting (подтравливающий) effect which results in anisotropic profile of an etched pattern.
Dry etch technologies available for LSI processing are classified into plasma etch, sputter etch and ion beam etch, with items such as etch mode, apparatus and reaction mechanism.
