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FAQ

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, . 2

 

 
 

 

. 2.

 

 

. 1.

 

 

1.

New
Open
Save
Print
Cut
Copy
Paste
Undo
Redo Undo
Zoom In
Zoom Out
Zoom Area
  Zoom All
Annotate
Back Annotate
Design Rules Check DRC ERC
Create Netlist EDIF 200, SPICE, VHDL, Verilog, Layout .
Cross Reference
Bill of Materials
Snap to Grid ( Options> Preierences > Grid Display)
Project manager
Help Topics ,

 

 

 

. 3. OrCAD Capture

 

. 2. OrCAD Capture .

 

2. OrCAD Capture

File ()
New... :
Project... (Analog or Mixed-Signal Circuit), (PC Board) (Schematic)
Design
Library
VHDL File VHDL
Text File
PSpice Library PSpice
Open :
Project... ( *.opj)
Design... ( *.dsn)
Library... ( *.olb)
VHDL File- VHDL ( *.vhd)
Text File... ( *.txt)
PSpice Library PSpice ( *.lib)
File ()
Close ( , )
Close Project
Save (Ctrl+S)
Save As... ,
Archive Project... (Library , Output files , Referenced projects )
Export Selection... ,
Import Selection...
Print Preview...
Print (Ctrl+P)
Print Setup... : , , (Landscape) (Portrait)
Import Design... EDIF, PDIF (P-CAD) PSpice Schematics
Export Design... EDIF DXF (AutoCAD)
1,
Exit (Alt+F4)
Edit ()
Undo ( )
Redo Undo ( )
Repeat (F4) ( )
Cut (Ctrl+X)
Paste
Delete (Del) ( )
Select All ,
Project...
Properties... (General , , , Project )
Link Database CIS
Derive Database Part...
Part
PSpice Model
Pspice Stimul      
Edit ()
Browse :
Parts
Nets
Flat Netlist ,
Hierarchical Ports
Off-Page Connectors
Title Blocks
Bookmarks
DRC Markers
Mirror :
Horizontally
Vertically
Both
Rotate 90
Group (, ..)
Ungroup
Find... (Ctrl+F) (Parts, Nets, Off-Page connectors, Hierarchical Parts, Bookmarks, DRC Markers, Text). . *,
Global Replace
Rename Part Property... ,
Delete Part Property... ,
Replace
Go To
Clear Session Log
View ()
Ascend Hierarchy
Descend Hierarchy
Convert ( )
Part
Package ( )
Next Part
Previous Part
Go To
View ()
Zoom :
In (I) ( )
Out () ( )
Scale...
Area
All
Selection ,
Redraw
Tool Palette
Toolbar
Status Bar
Grid
Grid Reference /
Database Part CIS
Place ()
Part... (Shift+P)
Database Part... CIS ( )
Wire (Shift+W) . Shift ( 90)
Bus (Shift+B) ( )
Junction
Bus Entry , 45
Net Alias ( )
Power...
Ground...
Off-Page Connector...
Hierarchical Block...
Hierarchical Port...
Hierarchical Pin...
No Connect
Pin...
Pin Array...
IEEE Symbol... IEEE
Title Block... ( )
Bookmark... , View>Go To
Text... (Shift+T) , , ( True , )
Line
Rectangle
Place ()
Ellipse
Arc
Polyline
Pictire... ( *.bmp)
Macro()
Configure... (F9) Configure Macro , , ,
Play (F8) , Configure Macro
Record (F7) , Configure Macro ( )
PSpice ()
New Simulation Profile ;
Edit Simulation Profile
Run (F11)
View Simulation Results (F12) ( Probe)
View Output File (*.OUT)
Create Netlist (*.NET)
View Netlist
Place Optimizer Parameters
Run Optimizer
Markers , , :
Voltage Level
Voltage Differential
Current into Pin
Power Dissipation
Advanced...
Plot Window Templates...
Show All
Hide All
Delete All
List...
PSpice ()
Bias Points
Enable
Enable Bias Current Display
Toggle Selected Bias Current
Enable Bias Voltage Display
Toggle Selected Bias Voltage
Enable Bias Power Display
Toggle Selected Bias Power
Preferences... ( , )
Accessories ()
Rotate Aliases
Allegro Netlist Allegro
Hierarchy Report
Associate DLL's DLL-
Options ( )
Preferences... . Color/Print, Grid Display, Pan and Zoom, Select, Miscellaneous, Text Editor , , . Run, Groups, Reports, Editor, Fonts, Colors , , .
Design Template... Fonts, Title Block, Page Size, Grid Reference, Hierarchy, SDT Compatibility
CIS Configuration... Capture CIS
Update Part Status (, CIS)
Design Properties ( Fonts. Hierarchy. SDT Compatibility. Miscellaneous)
Product Configuration : Capture Capture CIS, PSpice PSpice A/D
Schematic Page Properties... Page Size, Grid Reference, Miscellaneous
Part Properties...
Package Properties...
Window ()
New Window ,
Window ()
Cascade
Tile Horizontally
Tile Vertically
Arrange Icons
1. Session Log
2. < >.opj
3. < >
Help ()
Help Topics (F1) , OrCAD Capture
Learning Capture OrCAD Capture
About Capture
Web Resources :
OrCAD Home Page www.orcad.com
Customer Support www.orcad.com/technical
SpinCircuit Home www.spincircuit.com Page
PSpice PSpice
Help Topics , PSpice
About PSpice
OrCAD CIS CIS
Tools ()
Annotate... ( *.swp)
Update Properties... *.upd
Part Manager Capture CIS:
Open
Update
Design Rules Check... DRC ERC
Create Netlist... EDIF 2 0 0 ( *.edn), SPICE (*.cir, *.map), VHDL (*.vhd), Verilog (*.v), Layout (*'.mnl), PCB 386+ (*.net), VST (*.inf), OHDL (*.pld), XNF (*.xnf) . (Allegro, Altera, PADS, P-CAD, Tango,...)
Cross Reference (.xrf)
Bill of Materials... (*.bom)
Export Properties... ( ) . ( )
Import Properties
Generate Part
Reports ()
CIS Bill of Materials Capture CIS:
Standard...
Crystal Reports... Crystal Reports Seagate Technology
Variant Report...
Design ()
New Schematic...
New Schematic Page...
New VHDL File... VHDL-
New Part...
New Symbol...
Rename...
Delete (Del) VHDL-
Remove Occurrence Properties ,
Make Root
Replace Cache... , Design cache,
Update Cache , (design cache),
Cleanup Cache   ( , )
. (...) , .
                       

Capture. File , Hierarchy . :

Design Resource ( *.dsn, , Design Cache, VHDL-, *.olb);

Outputs ;

PSpice Resource PSpice (Include Files, Model Library, Simulation Profiles, Stimulus Files) .

( , ). , :

Add File ;

Part manager ;

Edit ;

Properties ;

New Schematic ;

Design Properties ;

Save - ;

Save As... ;

Simulate Selected Profile (s) PSpice ( );

View Simulation Results ;

View Output File ;

Edit Simulation Settings ;

Make Active ;

New Page ;

Edit Page ;

Schematic Page Properties ;

Edit Selected object properties ;

Make Root ;

Rename .

 

. 4 , (. 5), . 3 4.

 

 
 

. 4.

 

 
 

 

. 5.

 

 

3.

Select
Part
Wire . Shift
Net Alias ( )
Bus ( )
Junction
Bus Entry , 45
Power
  Ground
Hierarchical Block
Hierarchical Port
Hierarchical Pin
Off-Page Connector
No Connect ,
Line
Polyline
Rectangle
Ellipse /
Arc
Text , ,

 

 

4.

New Simulation Profile
Edit Simulation Setting
Run PSpice PSpice
View Simulation Results
Voltage/Level Marker /
Voltage Differential Markers
Current Marker
Power Dissipation Marker
Enable Bias Voltage Display
Toggle Voltage On Selected Net /
Enable Bias Current Display
Toggle Current On Selected Part/Pin /
Enable Bias Power Display
Toggle Power On Selected Part /

 

.

 

. 6 , (. 7), . 5.

 


. 6.

 

 
 

. 7.

 

5.

  IEEE Symbol IEEE
  Pin
  Pin Array

 

.

VHDL- . . 2.11 VHDL-, , Preferences Options. VHDL- , File>Open>Text File.

 

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Capture (. 8), , ( ), ( ), ( ).

 

 

. 8.


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