.


:




:

































 

 

 

 


6.3




6.3. 1. ,

() SiGe (. 6.5). , Si SiGe, . , .

. 6.5. () Si-SiGe.

, . , (. 6.6).

 

 

. 6.6 : ) " SiGe ) Si/SiGe (SGOI); ) (SSDOI).

 

(). SiGe (SGOI) (. 6.6), − (. 6.6). SiGe . Si/SiGe . SiGe , Si . Si/SiGe " SiGe ( Smart Cut). SiGe Si (SSDOI). 100%, 20-25%.

, SiGe . () . SiGe Si. , . , , . , Si/SiGe , SiGe.

6.3. 2. ,

, :

) Si3N4 (etch - stop liner - ), N- P - .

) "" (Stress Memorization Technique) N - .

) SiGe - .

) (SiN)

, , 90- . , , , Si, , , . , .

2000 [7]. - . . (I on). , . . , n - 11-15%, - ~20-25%.

. 6.7. Ge n -

 

-. -, -. . Ge (. 6.7).

, , "" - , -. " , " (Dual Stress Liner − DSL process). , p -. , n -. 12-24%. DSL [8-11].

 

) (Stress Memorization Technique)

. , / . (. 6.8). , , . "" . . . , , 15-20% .

. 6.8. ": ) - / ; ) - ; ) - .

 

) SiGe / -

- SiGe. , SiGe. n - , , SiGe. , SiGe , Si, , .

, SiGe, , Ge . . .

 

6.3.3

, , .

, - , (. 6.9).

. 6.9.

 

, 2,5 (110), (100). (110) . () . . 6.10 [12].

 

. 6.10. [12].

 

(Hybrid Orientation Technology − HOT). - n - (100), - (110).

HOT- . 6.11. (100) (110) " ". (100) (100). . , - - n - . , - (110) 18-21%. .

 

.6.11. : ) − (110) (100) ; ) − ; ) − (110) (100) ; ) − (100).

 

6.4

, , , . [13], , , 200%. [14]. : , SiGe /, . . , , .

90-65 . ITRS-2005(2006), () . , 65 , 90. , , , , . ITRS , .

2007 45 Intel. , c [15].

, , , . , .

- [16,17].

 

1. .. - -. 4.1. .: , 2002. . 2. 2004. 535 .

2. .. . . . 2006. 5. C. 35-44.

3. Skotnicki ., Monfray S. Materials and MOS device architectures for sub - 32 nm CMOS nodes ICMNE-2997 Oct. 1-5, 2007, Moscow-Zvenigorod, Russian. P. Ll-01.

4. .., .. - -.. , 2009, 38, 2, .83-98.

5. Smith C.S. Piezoresistance Effect in Germanium and Silicon // Phys. Rev. 1954,V. 94. 1. P. 4249.

6. 6.Arghani R. et al. Strain Engineering in Non - Volatile Memories. Sem. Intern. April 2006, .32.

7. S. et al. Mechanical stress effect of etch -stop nitride and its impact on deep submicron transistor design. IEDM Tech. Dig. Dec. 2000.

8. Yang Y.S. et al. IEDM Tech. Dig., Dec. 2004. P. 1075-78.

9. Shimitzu A. et al. Local mechanical-stress control (LMC): A new technique for CMOS-performance enhancement. IEDM Tech. Dig. Dec. 2003.

10. Ota K. et al. Novel Locally Strained Technique for Per-formanxe 55nm CMOS. IEDM Tech. Dig. Dec. 2002. P. 27-30.

11. Chen C.H. et al. VLSI Simpos. June. 2004. P. 56-57.

12.. Victor Chan et al. Strain for CMOS performance Improvement IEEE 2005 Custom Integrated Circuits conference.

13. Washington L. et al. p-MOSFET with 200% Mobility Enhancement Induced by Multiple Stressors // IEEE Electron Dev, Lett. June. 2006. V. 27.

14. Horstmann M. et al. Integration and Optimization of Embedded SiGe, Compressive and Tensile Stressed Liner Films, and Stress Memorization in Advanced SOI CMOS Technologies // IEDM Tech. Dig. Dec. 2005. Report 5. Session 10.

15. James D. Strained silicon to high-k and metal gate // Sol. St. Tech. Nov. 2007.

16. Sverdlov V. Strain-Induced Effect in Advanced MOSFETs, Springer-Verlag/Vien, 2011.

17. Scotnicki T., Fenouillet-Beranger C., Gallon C. at al. Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia, IEEE Transaction on Electron Devices, 2008, v.55, 1,pp.96-128.

 

 

1. ( 2).

2. , , , . , (.2) .., , .:, 2002, .19-56.

3. IV (. 104-111) [17] ( ). 111 ( ).

 

.


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