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// FILE: Lab9.c

// TITLE:DSP28 CAN

//CPU Timer0 ISR 50

//Watchdog , ISR

//CAN-: 1 ( GPIO B15-B8) 1

// 100KBPS

// : 0x1000 0000

// Mailbox #5

#include "DSP281x_Device.h" //

 

void Gpio_select(void);

void SpeedUpRevA(void);

void InitSystem(void);

void InitCan();

interrupt void cpu_timer0_isr(void);

// Timer 0

 

void main(void)

{

struct ECAN_REGS ECanaShadow;

 

InitSystem(); //

 

Gpio_select(); // /

InitPieCtrl();// PIE- (DSP281x_PieCtrl.c)

 

InitPieVectTable(); // PIE- (DSP281x_PieVect.c)

 

// PIE Timer 0

EALLOW; // EALLOW

PieVectTable.TINT0 = &cpu_timer0_isr;

EDIS; // EALLOW

 

InitCpuTimers();

 

// CPU-Timer 0 50 :

// 150MHz CPU, 50000

ConfigCpuTimer(&CpuTimer0, 150, 50000);

 

// TINT0 PIE: 1 7

PieCtrlRegs.PIEIER1.bit.INTx7 = 1;

 

// CPU INT1 CPU-Timer 0:

IER = 1;

 

// :

EINT; // INTM

ERTM; // DBGM

 

InitCan();

/* MSGID */

ECanaMboxes.MBOX5.MSGID.all = 0x????????;

ECanaMboxes.MBOX5.MSGID.bit.IDE =?; //

 

/* Mailbox 5 */

ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;

ECanaShadow.CANMD.bit.MD5 =?;

ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;

/* Mailbox 5 */

ECanaShadow.CANME.all = ECanaRegs.CANME.all;

ECanaShadow.CANME.bit.ME5 =?;

ECanaRegs.CANME.all = ECanaShadow.CANME.all;

 

/* 1 */

ECanaMboxes.MBOX5.MSGCTRL.bit.DLC =?;

CpuTimer0Regs.TCR.bit.TSS = 0;

while(1)

{

while(CpuTimer0.InterruptCount < 20)

{ // Timer 0

EALLOW;

SysCtrlRegs.WDKEY = 0xAA; // watchdog #2

EDIS;

}

CpuTimer0.InterruptCount = 0; //

ECanaMboxes.MBOX5.MDL.byte.BYTE0 = (GpioDataRegs.GPBDAT.all>>8);

ECanaShadow.CANTRS.all =?;

ECanaShadow.CANTRS.bit.TRS5 =?; // Mailbox 5

ECanaRegs.CANTRS.all = ECanaShadow.CANTRS.all;

 

while(ECanaRegs.CANTA.bit.TA5 == 0) {} // TA5 ..

 

ECanaShadow.CANTA.all =?;

ECanaShadow.CANTA.bit.TA5 =?; // TA5

ECanaRegs.CANTA.all = ECanaShadow.CANTA.all;

}

}

 

void Gpio_select(void)

{

EALLOW;

GpioMuxRegs.GPAMUX.all = 0x?; // /

GpioMuxRegs.GPBMUX.all = 0x?;

GpioMuxRegs.GPDMUX.all = 0x?;

GpioMuxRegs.GPFMUX.all = 0x?;

GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6 =?; // CANTXA

GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7 =?; // CANRXA CAN-

GpioMuxRegs.GPEMUX.all = 0x?;

GpioMuxRegs.GPGMUX.all = 0x?;

GpioMuxRegs.GPADIR.all = 0x?; // , D, E, F, G

GpioMuxRegs.GPBDIR.all = 0x????; // 15-8 , 7-0

GpioMuxRegs.GPDDIR.all = 0x?;

GpioMuxRegs.GPEDIR.all = 0x?;

GpioMuxRegs.GPFDIR.all = 0x?;

GpioMuxRegs.GPGDIR.all = 0x?;

 

GpioMuxRegs.GPAQUAL.all = 0x?; //

GpioMuxRegs.GPBQUAL.all = 0x?;

GpioMuxRegs.GPDQUAL.all = 0x?;

GpioMuxRegs.GPEQUAL.all = 0x?;

EDIS;

}

 

void InitSystem(void)

{

EALLOW;

SysCtrlRegs.WDCR= 0x00AF; //

// 0x00E8 , = 1

// 0x00AF , = 64

SysCtrlRegs.SCSR = 0; // WDT

SysCtrlRegs.PLLCR.bit.DIV = 10; //

SysCtrlRegs.HISPCP.all = 0x1; //

SysCtrlRegs.LOSPCP.all = 0x2; //

// eCAN

SysCtrlRegs.PCLKCR.bit.EVAENCLK=0;

SysCtrlRegs.PCLKCR.bit.EVBENCLK=0;

SysCtrlRegs.PCLKCR.bit.SCIAENCLK=0;

SysCtrlRegs.PCLKCR.bit.SCIBENCLK=0;

SysCtrlRegs.PCLKCR.bit.MCBSPENCLK=0;

SysCtrlRegs.PCLKCR.bit.SPIENCLK=0;

SysCtrlRegs.PCLKCR.bit.ECANENCLK=1;

SysCtrlRegs.PCLKCR.bit.ADCENCLK=0;

EDIS;

}

interrupt void cpu_timer0_isr(void)

{

CpuTimer0.InterruptCount++; // watchdog- Timer 0

EALLOW;

SysCtrlRegs.WDKEY = 0x55; // watchdog #1

EDIS;

// 1

PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;

}

void InitCan(void)

{

asm(" EALLOW");

/* TX RX eCAN*/

ECanaRegs.CANTIOC.bit.TXFUNC =?;

ECanaRegs.CANRIOC.bit.RXFUNC =?;

/* eCAN HECC - ( mailboxes 16 - 31) */

// HECC

ECanaRegs.CANMC.bit.SCB =?;

/* */

ECanaRegs.CANMC.bit.CCR =?; // CCR

while(ECanaRegs.CANES.bit.CCE!= 1) {} // ( CAN)..

ECanaRegs.CANBTC.bit.BRPREG =??; // BRP,TSEG1 TSEG2

ECanaRegs.CANBTC.bit.TSEG2REG =?; // ,

ECanaRegs.CANBTC.bit.TSEG1REG =??; // 100/

 

ECanaRegs.CANMC.bit.CCR =?; // CCR CANMC CANBTC

while(ECanaRegs.CANES.bit.CCE ==!0) {} // CCE ..

}

/* Mailboxes */

//=================================================

// .

//=================================================

 

 

 

// FILE: Lab10.c

// TITLE: DSP28 CAN , Mailbox 1

// 0x10 000 000; 100 KBPS

// 1 CAN 8 LED's (GPIOB7 - B0)

// Watchdog , ISR

 

#include "DSP281x_Device.h" //

 

void Gpio_select(void);

void InitSystem(void);

void InitCan(void);

 

void main(void)

 

{

struct ECAN_REGS ECanaShadow;

 

InitSystem(); //

Gpio_select(); // /

InitCan();

 

/* MSGID - MBX MSGID */

ECanaMboxes.MBOX1.MSGID.all = 0x????????; //

ECanaMboxes.MBOX1.MSGID.bit.IDE =?;

 

/* Mailbox 1 */

ECanaShadow.CANMD.all = ECanaRegs.CANMD.all;

ECanaShadow.CANMD.bit.MD1 =?;

ECanaRegs.CANMD.all = ECanaShadow.CANMD.all;

 

/* Mailbox 1 */

ECanaShadow.CANME.all = ECanaRegs.CANME.all;

ECanaShadow.CANME.bit.ME1 =?;

ECanaRegs.CANME.all = ECanaShadow.CANME.all;

while(1)

{

do

{

ECanaShadow.CANRMP.all = ECanaRegs.CANRMP.all;

EALLOW;

SysCtrlRegs.WDKEY = 0x55; // watchdog #1

SysCtrlRegs.WDKEY = 0xAA; // watchdog #2

EDIS;

}

while(ECanaShadow.CANRMP.bit.RMP1!= 1); // RMP1 ..

 

GpioDataRegs.GPBDAT.all = ECanaMboxes.MBOX1.MDL.byte.BYTE0;

ECanaShadow.CANRMP.bit.RMP1 =?;

ECanaRegs.CANRMP.all = ECanaShadow.CANRMP.all;

// Clear RMP1 bit and start again

}

}

 

void Gpio_select(void)

{

EALLOW;

GpioMuxRegs.GPAMUX.all = 0x?; // /

GpioMuxRegs.GPBMUX.all = 0x?;

GpioMuxRegs.GPDMUX.all = 0x?;

GpioMuxRegs.GPFMUX.all = 0x?;

GpioMuxRegs.GPEMUX.all = 0x?;

GpioMuxRegs.GPGMUX.all = 0x?;

GpioMuxRegs.GPFMUX.bit.CANTXA_GPIOF6 =?; // CANTA CANRA

GpioMuxRegs.GPFMUX.bit.CANRXA_GPIOF7 =?;

 

GpioMuxRegs.GPADIR.all = 0x?; // , D, E, F, G

GpioMuxRegs.GPBDIR.all = 0x????; // 15-8 , 7-0

GpioMuxRegs.GPDDIR.all = 0x?;

GpioMuxRegs.GPEDIR.all = 0x?;

GpioMuxRegs.GPFDIR.all = 0x?;

GpioMuxRegs.GPGDIR.all = 0x?;

 

GpioMuxRegs.GPAQUAL.all = 0x?; //

GpioMuxRegs.GPBQUAL.all = 0x?;

GpioMuxRegs.GPDQUAL.all = 0x?;

GpioMuxRegs.GPEQUAL.all = 0x?;

EDIS;

}

 

void InitSystem(void)

{

EALLOW;

SysCtrlRegs.WDCR= 0x00AF; //

// 0x00E8 , = 1

// 0x00AF , = 64

 

SysCtrlRegs.SCSR = 0; // WDT

SysCtrlRegs.PLLCR.bit.DIV = 10; //

SysCtrlRegs.HISPCP.all = 0x1; //

SysCtrlRegs.LOSPCP.all = 0x2; //

 

// AN

SysCtrlRegs.PCLKCR.bit.EVAENCLK=0;

SysCtrlRegs.PCLKCR.bit.EVBENCLK=0;

SysCtrlRegs.PCLKCR.bit.SCIAENCLK=0;

SysCtrlRegs.PCLKCR.bit.SCIBENCLK=0;

SysCtrlRegs.PCLKCR.bit.MCBSPENCLK=0;

SysCtrlRegs.PCLKCR.bit.SPIENCLK=0;

SysCtrlRegs.PCLKCR.bit.ECANENCLK=1;

SysCtrlRegs.PCLKCR.bit.ADCENCLK=0;

EDIS;

}

 

void InitCan(void)

{

asm(" EALLOW");

/* TX RX eCAN*/

 

ECanaRegs.CANTIOC.bit.TXFUNC =?;

ECanaRegs.CANRIOC.bit.RXFUNC =?;

 

/* eCAN HECC - ( mailboxes 16 - 31) */

// HECC

ECanaRegs.CANMC.bit.SCB =?;

 

/* */

ECanaRegs.CANMC.bit.CCR =?; // CCR

while(ECanaRegs.CANES.bit.CCE!= 1) {} // CCE ( CAN) ..

ECanaRegs.CANBTC.bit.BRPREG =??;

ECanaRegs.CANBTC.bit.TSEG2REG =?;

ECanaRegs.CANBTC.bit.TSEG1REG =??;

 

ECanaRegs.CANMC.bit.CCR =?; // CCR CANM CANBTC

while(ECanaRegs.CANES.bit.CCE ==!0) {} // CCE ..

 

/* Mailboxes */

 

ECanaRegs.CANME.all =?; // Mailboxs

asm(" EDIS");

}

//===========================================================

// .

//===========================================================

 

:

 

, , , CAN-, , .

 

:

 

1. CAN- DSP TMS320F2812.

2. CAN.

3. CAN.

4. CAN.

5. CAN.

6. eCAN.

7. Mailbox .

 





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