DESIGNLAB
Schematics, :
- ANALOG.slb (R, L, );
- BIPOLAR.slb ;
- EDIODE.slb ;
- JFET.slb ;
- PORT.slb ( AGND ).
, - DesignLab . EVAL.slb. VDC ( ), SOURCE.slb. VDC DC. , SOURCE.slb.
, . , , VSIN ( ). VSIN , . 2-1, .
. 2-1. () V2 ()
Analysis Setup (Transient) , 1015 .
. 2-2. Transient
VAMPL = 5, FREQ = 5k, TD = 2ms, DF = 30, PHASE = 180 , VSIN.
. 2-3. : - VPULSE, - VEXP - VPWL_FILE
: VPULSE - (. 2-3, ), VEXP - (. 2-3, ) VPWL_FILE - , (. 2-3, ), , , . . VPULSE:
(1);
V1 (0);
V2 (2);
TD (0);
TR (0);
|
|
TF (0);
PW (lm);
PER (4).
VSIN PULSE , . V1 = 2, V2 = 5, TD = 2ms, TR = 0,2m, TF = 0,5m, PW = 2m, PER = 5m , VPULSE.
VEXP:
(1);
V1 (0);
V2 (1);
TD1 (0);
1 , 0.63*V2 (0.2m);
TD2 (2m);
2 , V2-0,63*V2 (0,2m).
VPULSE VEXP , . V1 = 1, V2 = 3, TD1 = 1ms, TC1 = 0,3m, TD2 = 4m, TC2 = 0,3m , VEXP.
VPWL_FILE:
(1);
TSF (1);
VSF (1);
FILE (primer.txt);
REPEAT_VALUE (3).
VPWL_FILE ( txt). :
(< 1>, < 1>)
(< 2>, < 2>)
..
(< N>, < N>)
, . .
. 2-4.
, . p4.sch , , .
, DesignLab Stimulus Editor, . VPWL_FILE, .
() , , .