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ALDEC HDL
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ALDEC HDL
1 : ALDEC HDL.
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VHDL. , VHDL, CAD-.
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Aldec HDL VHDL , . FPGA.
Aldec HDL :
1. VHDL .
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3. Aldec .
VHDL FPGA Express, , FPGA Express . FPGA Express , . . :
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HDL.
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FPGA Express , VHDL . , , VHDL . FPGA Express . , , , VHDL, .
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HDL . , . , HDL , , .
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ALDEC HDL
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1. () VHDL . , : *.vhd.
2. Aldec HDL.
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1. Aldec HDL - Workspace ( 1).
File > New > Workspace.
1 .
2. , *.vhd.
3. . ( 2).
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8-
8- - D- ( ). D- DFF. SHIFT - D- ( ).
DFF () , .
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port map.
(. bit0, biti, bit2, bit3, bit5, bit6), (. bit6, bit7).
open.
VHDL- , addl b1 0 1 .
P1: addlport map (bl => '0', b2 => x, sl => sl, 1 => open);
VHDL
Library IEEE;
library synopsys;
use IEEE.std_logic_1164.all;
use synopsys.attributes.all;
entity DFF is -- D - trigger
port(
RSTn, CLK, D: in bit;
Q: out bit);
end DFF;
architecture RTL of DFF is -- Functional D-trigger
begin
process (RSTn, CLK)
begin
if (RSTn = '0') then
Q <= '0';
elsif (CLK'event and CLK = '1') then
Q <= D;
end if;
end process;
end RTL;
entity SHIFT is -- SHIFT 8-bit trigger
port(
RSTn, CLK, SI: in bit;
SO: out bit);
end SHIFT;
architecture RTL1 of SHIFT is
component DFF
port(RSTn, CLK, D: in bit;
Q: out bit);
end component;
signal T: bit_vector(6 downto 0);
begin
bit7: DFF
port map (RSTn =>RSTn, CLK =>CLK, D =>SI, Q =>T(6));
bit6: DFF
port map (RSTn, CLK, T(6), T(5));
bit5: DFF
port map (RSTn, CLK, T(5), T(4));
bit4: DFF
port map (CLK=>CLK, RSTn=>RSTn, D=>T(4), Q=>T(3));
bit3: DFF
port map (RSTn, CLK, T(3), T(2));
bit2:DFF
port map (RSTn, CLK, T(2), T(1));
bit1: DFF
port map (RSTn, CLK, T(1), T(0));
bit0: DFF
port map (RSTn, CLK, T(0), SO);
end RTL1;
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Active-HDL. , .
