- UART (Universal Asynchronous Receiver-Transmitter ). . - IBM PC XT/AT , UART i8250 8250/16450/16550. , , . , :
♦ 8250 ( ), XT BIOS;
♦ 8250 , BIOS; AT, 9600 /;
♦ 8250 8250 8250A, XT BIOS; AT DOS ( 9600 /).
8250x . CPU. AT UART .
♦ 16450 8250 AT. 8250 XT BIOS .
♦ 16550 16450. DMA . FIFO-, .
♦ 16550 16- FIFO- DMA. UART AT 9600 / . -, .
UART 16550 , ( ) DLAB ( 7 LCR). 8 . UART 16550A . 2.4. 8250 FCR FIFO DMA.
2.4. UART 16550A
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| DLAB | ||||||
| 0h | 0 | THR | Transmit Holding Register | WO | ||
| 0h | 0 | RBR | Receiver Buffer Register | RO | ||
| 0h | 1 | DLL | Divisor Latch LSB | R/W | ||
| 1h | 1 | DIM | Divisor Latch MSB | R/W | ||
| 1h | 0 | IER | Interrupt Enable Register | R/W | ||
| 2h | x | IIR | Interrupt Identification Register | RO | ||
| 2h | x | FOR | FIFO Control Register | WO | ||
| 3h | x | LCR | ||||
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¹ . .
HR ( ). , , ( ), CTS. 0 ( ) . 8 .
RBR ( ). , , RBR, . , . 8 .
DLL .
DLM . D=115200/V, V , /. 1,8432 , 16- .
IER . .
IER:
♦ [7:4]=0 ;
♦ 3 Mod_IE ( CTS, DSR, RI, DCD);
♦ 2 RxL_I / ;
♦ 1 TxD_IE ;
♦ 0 RxD_I ( FIFO -).
IIR FIFO ( ). UART . ( ): , , , . UART , . . IIR.
♦ [7:6] FIFO:
11 FIFO 16550A;
10 FIFO 16550;
00 .
♦ [5:4] .
♦ 3 - FIFO ( ).
♦ [2:1] ( , FIFO-):
11 / , ;
10 , ;
01 ( THR ), ;
00 ; .
♦ 0 (1 , 0 ).
FIFO [3:1].
♦ 011 / . .
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♦ 010 . .
♦ 110 - ( 4- , , , ). .
♦ 001 THR . .
♦ 000 (CIS, DSR, RI DCD). MSR.
FCR FIFO ( ). FCR:
♦ [7:6] ITL (Interrupt Trigger Level) FIFO-, :
00 1 ( );
01 4 ;
10 8 ;
1114 .
♦ [5:4] .
♦ 3 DMA.
♦ 2 RESETTF (Reset Transmitter FIFO) FIFO- ( ; ).
♦ 1 RESETRF (Reset Receiver FIFO) FIFO- ( ; ).
♦ 0 TRFIFOE (Transmit And Receive FIFO Enable) () FIFO . FIFO- .
LCR ( ). LCR.
♦ 7 DLAB (Divisor Latch Access Bit) .
♦ 6 BRCON (Break Control) ( ) BRCON=1.
♦ 5 STICPAR (Sticky Parity) :
0 ;
1 : EVENPAR=1 , EVENPAR=0 .
♦ 4 EVENPAR (Even Parity Select) : 0 , 1 .
♦ 3 PAREN (Parity Enable) :
1 ( ) ;
0 .
♦ 2 STOP (Stop Bits) -:
01 -;
12 - ( 5- - 1,5 ).
♦ [1:0] SERIALDB (Serial Data Bits) :
00 5 ;
01 6 ;
10 7 ;
11 8 .
MCR . MCR.
♦ [7:5]=0 .
♦ 4 LME (Loopback Mode Enable) :
0 ;
1 (. ).
♦ 3 IE (Interrupt Enable) OUT2; MSR.7:
0 ;
1 .
♦ 2 OUT1C (OUT1 Bit Control) 1 ( ); MSR.6.
♦ 1 RTSC (Request To Send Control) RTS; MSR.4:
0 (-V);
1 (+V).
♦ 0 DTRC (Data Terminal Ready Control) DTR; MSR.5:
0 (-V);
1 (+V).
LSR (, ). LSR.
♦ 7 FIFOE (FIFO Error Status) FIFO ( , , ). FIFO- 0.
♦ 6 TEMPT (Transmitter Empty Status) ( , THR FIFO).
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♦ 5 THRE (Transmitter Holding Register Empty) . FIFO FIFO- . .
♦ 4 BD (Break Detected) ( 0 ).
♦ 3 FE (Framing Error) ( -).
♦ 2 (Parity Error) ( ).
♦ 1 (Overrun Error) ( ). , FIFO, .
♦ 0 DR (Receiver Data Ready) ( DHR FIFO- ). .
[4:1] LSR. FIFO FIFO- . ( ) , , , FIFO ( ). FIFO , UART -.
MSR . MSR:
♦ 7 DCD (Data Carrier Detect) DCD:
0 (-V);
1 (+V).
♦ 6 RI (Ring Indicator) RI:
0 (-V);
1 (+V).
♦ 5 DSR (Data Set Ready) DSR:
0 (-V);
1 (+V).
♦ 4 CTS (Clear To Send) CTS:
0 (-V);
1 (+V).
♦ 3 DDCD (Delta Data Carrier Detect) DCD.
♦ 2 RI (Trailing Edge Of Ring Indicator) RI ( ).
♦ 1 DDSR (Delta Data Set Ready) DSR.
♦ 0 DCTS (Delta Clear To Send) CTS.
( [3:0]) .
SCR (8 ), UART , ( 8250 ).
( LME=1) UART :
♦ ;
♦ ;
♦ ;
♦ DSR, CIS, RI DCD DTRC, RISC, OUT1C, IE;
♦ ( ).
, ( ) , UART.
