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FAQ

2. Verilog

⇐ 123 ⇒



 

Verilog. . Verilog . , , . Verilog, Verilog.

Verilog Verilog, Verilog-XL simulator. , $, Verilog-XL simulator Verilog.

Verilog . , , Verilog. , Verilog - , , . , , .

 

 

(module) Verilog. , . , , 32- , , .

, , (. 2.1).

add2bit . (wire). . , "always... begin" "end". , , .

,----------------------------------------------------------.

| module add2bit (in1, in2, sum); |

| input in1, in2; |

| output[1:0] sum; |

| wire inl, in2; |

| reg[1:0] sum; |

| |

| always @ (inl or in2) begin |

| sum = inl + in2; |

| $display ("The sum of %b and %b is %0d (time = %0d)",|

| inl, in2, sum, $time); |

| end |

| endmodule |

`----------------------------------------------------------'

.2.1

add2bit , , . . 2.2 .

(header), (module name) . , . () , () . (wire), , , .

 

,-------------------------------------------------------------.

| module <_> < />; |

| < /> |

| < > |

| |

| <_> |

|... |

| <_> |

| |

| endmodule |

`-------------------------------------------------------------'

 

.2.2

 

.2.3 <_>. , , .

- . ,

wire[7:0] result;

assign result = op1 + op2;

wire[7:0] result = op1 + op2;

result op1 op2. , op1 op2 , result .

- . ,

fulladd f1 (cin0, a0, b0, sum0, cout0);

fulladd f2 (cout0, a1, b1, sum1, cout2);

fulladd , f1 f2. . , .

, . - Verilog, AND, OR .. , , Verilog, , .

Verilog, "initial" "always". ( , ) . "initial" . ,

initial

i = 0;

i 0 . "always" . ,

always

#10 i = i + 1;

i 1 10 .

Verilog.

 

 

 

, Verilog , , (variables), . Verilog , ,

 

'

 

- , , - , b,B,d,D,o,O,h H.

b ,

,

D d ,

H h .

B b , o , D d , H h .

, , , . :

 

15 ( 15)

'h15 ( 21, 15)

5'b10011 ( 19, 10011)

12'h01F ( 31, 01F)

 

(, "mystring") ASCII. , "ab" 16'h5758.

Verilog reg (), wire (), integer (), real (), event () time (). integer, float, time event , reg wire . Wire , reg . reg, wire , 1. reg wire : 1, 0, x z. , , , . z . reg wire .

:

 

integer i, j; //

real f, d; //

wire [7:0] bus; // 8-

// bus ()

reg [0:15] word; // 16-

// word ()

event trigger,clock_high; //

time t_setup,t_hold; // t1, t2

 

C reg wire :

reg [15:0] word;

reg [7:0] byte;

...

word[0] =... //

// word

byte =... +word[15:8]; // word

... word... // word[15:0]

Verilog:

 

i = i + j;

assign bus = word[15:8] + word[7:0];

f = (g + 1.2) * 3.29E-5;

@e1 #5 ->e2; // 1

// 5

// 2

if ($time - t1 < t2) error ("timing violations");

 

- 32- , . time 64- . event time " ".

Verilog , array (), . :

 

integer num[99:0]; // 100

reg [7:0]mem[0:1024]; // 1024

reg [10*8:1]names[20]; // 20

// names,

// 10 ,

// 8-

 

, , word[i] i- word i- word, , word. :

 

reg [15:0] array [0:10];

reg [15:0]temp;

...

temp = array[3];

...temp[7:5]

 

 

 

Verilog . (++) (--). .2.3 Verilog. .2.6 .

 

,----------------------------------------------------.

| + - * / ( ) |

| > >= < <= ( ) |

|! && || ( ) |

| ==!= ( ) |

|?: () |

| { } () |

| % ( " ") |

| ===!== () |

| ~ & | (-) |

| << >> () |

`----------------------------------------------------'

 

.2.3

 

. , "+varname" varname. "^varname", varname, .

^word === 'bx // , word ,

//

&word == 0 // , word ,

// 0

 

 

-----------. ||, && |, &

 

| -------------------------------------

. | 1) &,|

-----------' , ,

-

& |. - -

.

2) &&, || : -

,

1, - 0, -

& |

; -

.

 

 

. , 0 1 ( z) . , z, Verilog "===" "!==". .2.4 "==" "===".

,-------------------------------------------------------.

| module equ_equ; |

| |

| initial begin |

| $display ("'bx == 'bx is %b", 'bx == 'bx); |

| $display ("'bx === 'bx is %b", 'bx === 'bx); |

| $display ("'bz!= 'bx is %b", 'bz!= 'bx); |

| $display ("'bz!== 'bx is %b", 'bz!== 'bx); |

| end |

| |

| endmodule |

`-------------------------------------------------------'

 

.2.4 " == " " ==="

 

equ_equ :

 

'bx == 'bx is x

'bx === 'bx is 1

'bz!= 'bx is x

'bz!== 'bx is 1

 

, , . ( ) { }, :

 

{2'b1x, 4'h7} === 6'b1x0111

 

. , , ( 1'bz, 'bz). .

. :

{3{2'b01}} === 6'b010101

.2.5 word.

,----------------------------------------------.

| module concat_replicate(swap,signextend); |

| |

| input swap,signextend; |

| |

| reg[15:0] word; |

| reg[31:0] double; |

| reg[7:0] byte1, byte2; |

| |

| initial begin |

| byte1 = 5; byte2 = 7; |

| if(swap) |

| word = {byte2, byte1}; |

| else |

| word = {byte1, byte2}; |

| if(signextend) |

| double = {{16{word[15]}},word}; |

| else |

| double = word; |

| end |

| |

| endmodule |

`----------------------------------------------'

.2.5

 

, . .

 

 

, , . . , "begin" "end". . :

begin: instruction_fetch

...

end

, ":" - . .

,---------------------------------------------------.

| binary op. |

|!~ |

| * / % |

| + - |

| << >> |

| < <= > >= |

| ==!= ===!== |

| & |

| ^ ^~ |

| | |

| && |

| || |

|?: |

`---------------------------------------------------'

.2.6

 

Verilog , .

 

for

 

C (.2.7) for.

for_loop :

i = 0 (0 )

i = 1 (1 )

i = 2 (10 )

i = 3 (11 )

,---------------------------------------------------.

| module for_loop |

| |

| integer i; |

| |

| initial |

| for (i = 0; i < 4; i = i + 1) begin |

| $display ("i = %0d (%b binary)", i, i); |

| end |

| |

| endmodule |

`---------------------------------------------------'

.2.7 for

 

c while

 

for while, .2.8. while loop , for loop . 2.7.

 

 

(.2.9) . switch .

,--------------------------------------------------.

| module while_loop |

| integer i; |

| initial begin |

| i = 0; |

| while (i < 4) begin |

| $display ("i = %0d (%b binary)", i, i);|

| i = i + 1; |

| end |

| end |

| endmodule |

`--------------------------------------------------'

.2.8 while

,--------------------------------------.

| module case_statement; |

| integer i; |

| initial i = 0; |

| always begin |

| $display ("i = %0d", i); |

| case (i) |

| 0: i = i + 2; |

| 1: i = i + 7; |

| 2: i = i - 1; |

| default: $stop; |

| endcase |

| end |

| endmodule |

`--------------------------------------'

.2.9

 

case statement :

 

i = 0

i = 2

i = 1

i = 8

 

( ) ( ":"), ( ===). , (default).

, . . , .

casez casex case, . casez , z, casex , z x.

 

repeat

 

Verilog , . .2.10 repeat, 5 , .

 

forever

 

.2.11 forever, , .

repeat forever , , for, , . , .

,------------------------------------.

| module repeat_loop (clock); |

| input clock; |

| |

| initial begin |

| repeat (5) |

| @ (posedge clock); |

| $stop; |

| end |

| |

| endmodule |

`------------------------------------'

 

.2.10 repeat

 

,----------------------------------------------------.

| module forever_statement (a,b,c); |

| input a,b,c; |

| |

| initial forever begin |

| @ (a or b or c) |

| if (a + b == c) begin |

| $display ("a(%d)+b(%d) = c(%d)", a,b,c);|

| $stop; |

| end |

| end |

| |

| endmodule |

`----------------------------------------------------'

 

.2.11 forever

 

Verilog . . , . , , , Verilog . . , . Verilog simulator .

Verilog simulator , . , , . (, , ). .2.12 , . , , , .

, , , Verilog simulator . , Verilog , , , . , . .2.13 .

 

t1 t2 t3

-----------,----------------,----------------,------->

| | |

,-----'-----.,-----'-----.,-----'-----.

| 0 | | 3 | | 4 |

`-----,-----' `-----------' `-----,-----'

,-----'-----.,-----'-----.

| 1 | | 5 |

`-----,-----' `-----------'

,-----'-----.

| 2 |

`-----------'

 

.2.12

,--------------------------------------------------------.

| module event_control; |

| |

| register [4:0] r; |

| |

| initial begin |

| $display ("First initial block, line 1."); |

| $display ("First initial block, line 2."); |

| end |

| |

| initial |

| for (r = 0; r <= 3; r =r + 1) |

| $display ("r = %0b",r); |

| |

| endmodule |

`--------------------------------------------------------'

 

.2.13

 

event_control :

Fist initial block, line 1.

Fist initial block, line 2.

r = 0

r = 1

r = 10

r = 11

 

, initial ( 0).

.2.13, , Verilog , . , , , .

 

 

Verilog ( initial always) :

 

#

@-

wait ()

 

#, , , "", @-, , , . .

wait () - , . wait , , (- ).

.2.14 .

time_control :

r = 2 5

r = 1 10

r = 2 25

r = 1 30

r = 2 55

r = 1 60

 

 

, initial

 

initial #70 $stop;

 

- .

, initial , ( ) . (b1 b2). , , .

@- , , , . :

) < >....

b) posedge

c) negedge

d) -

 

) , . b) ) , 0, z

,-----------------------------------------------------.

| module time_control; |

| |

| reg[1:0] r; |

| |

| initial #70 $stop; |

| |

| initial begin: b1 // b1 |

| #10 r = 1; // 10 |

| #20 r = 1; // 20 |

| #30 r = 1; // 30 |

| end |

| |

| initial begin: b2 // b2 |

| #5 r = 2; // 5 |

| #20 r = 2; // 20 |

| #30 r = 2; // 30 |

| end |

| |

| always @r begin |

| $display ("r = %0d at time %0d", r, $time); |

| end |

| |

| endmodule |

`-----------------------------------------------------'

.2.14

 

1 ( posedge) 1, z 0 ( negedge). d) , .

 

,-------------------------------------------------------.

| module event_control; |

| |

| event e1,e2; |

| |

| initial @e1 begin |

| $display ("I am in the middle."); |

| ->e2; |

| end |

| |

| initial @e2 |

| $display ("I am supposed to execute last."); |

| |

| initial begin |

| $display ("I am the first."); |

| ->e1; |

| end |

| |

| endmodule |

`-------------------------------------------------------'

.2.15

 

->c-. .2.15 - initial, .

event_control :

 

I am the first.

I am in the middle.

I am supposed to execute last.

 

. Verilog initial .

.

current_state = #clock_period next_state;

temp = next_state;

#clock_period current_state = next_state;

, ,

current_state = @ (posedge clock) next_state;

temp = next_state;

@ (posedge clock) current_state = temp;

 

 

Verilog , . - - (fork-join), - (disable statement).

 

fork-join

 

.2.16 -.

initial , b. (fork) . , (join). , .

,------------------------------------------.

| module fork_join; |

| |

| event a, b; |

| |

| initial |

| fork |

| @a; |

| @b; |

| join |

| end |

| |

| endmodule |

`------------------------------------------'

.2.16

 

 

, break . break , disable . , , . . .2.17 - , b, - , b.

,------------------------------------------.

| module disable_block; |

| event a, b; |

| // |

| initial begin: block1 |

| fork |

| @a disable block1; |

| @b disable block1; |

| join |

| end |

| endmodule |

`------------------------------------------'

.2.17

 

 

Verilog - (task) (function). .2.19 .

,-------------------------------------------------.

| function [7:0] func; |

| input i1; |

| integer i1; |

| |

| reg [7:0] rg; |

| |

| begin |

| rg=1; |

| for (i=1; i<=i1; i++) |

| rg=rg+1; |

| func=rg; |

| end |

| endfunction |

`-------------------------------------------------'

.2.18

 

,-----------------------------------------------------.

| task tsk; |

| |

| input i1,i2; |

| output o1,o2; |

| |

| $display ("Task tsk, i1=%0b, i2=%0b", i1,i2); |

| #1 o1 = i1 & i2; |

| #1 o2 = i1 | i2; |

| |

| endtask |

`-----------------------------------------------------'

.2.19

 

.

, . , ( ), , , , , , . , , .

, , . .

- , , . ,

tsk (out, in1, in2);

tsk,

i = func (a, b, c); //

assign x = func (y);

func.

.2.18 . . , . - . , , . . , , , . , , .

 

 

Verilog - , , . 4- .

.2.20 4- Verilog.

, sum zero . , . , initial always.

@(in1 in2) , in1 in2 . always .

, always initial, forever, .2.21.

,----------------------------------------------------.

| module adder4 (in1,in2,sum,zero); |

| |

| input [3:0] in1; |

| input [3:0] in2; |

| output [4:0] sum; |

| output zero; |

| reg [4:0] sum; |

| reg zero; |

| |

| initial begin |

| sum = 0; |

| zero = 1; |

| end |

| |

| always @ (in1 or in2) begin |

| sum = in1 + in2; |

| if (sum == 0) |

| zero = 1; |

| else |

| zero = 0; |

| end |

| endmodule |

`----------------------------------------------------'

.2.20 4-

 

.2.22 .2.20, adder4, .

zero , . sum , zero , "?:", , , , --. zero :

wire zero = (sum == 0)? 1: 0;

,----------------------------------------------.

| initial begin |

| forever begin |

| @ (in1 or in2) begin |

| sum = in1 + in2; |

| if (sum == 0) |

| zero = 1; |

| else |

| zero = 0; |

| end |

| end |

| end |

`----------------------------------------------'

.2.21 initial-forever always

 

,-----------------------------------------------.

| module adder4 (in1,in2,sum,zero); |

| input [3:0] in1; |

| input [3:0] in2; |

| output [4:0] sum; |

| reg [4:0] sum; |

| output zero; |

| |

| assign zero = (sum == 0)? 1: 0; |

| |

| initial sum = 0; |

| |

| always @ (in1 or in2) |

| sum = in1 + in2; |

| endmodule |

`-----------------------------------------------'

.2.22

 

 

.2.23 4- , 1- .

,------------------------------------------------------.

| module adder4 (in1,in2,sum,zero); |

| |

| input [3:0] in1; |

| input [3:0] in2; |

| output [4:0] sum; |

| output zero; |

| |

| fulladd u1 (in1[0],in2[0], 0,sum[0],c0); |

| fulladd u2 (in1[1],in2[1],c0,sum[1],c1); |

| fulladd u3 (in1[2],in2[2],c1,sum[2],c2); |

| fulladd u4 (in1[3],in2[3],c2,sum[3],sum[4]); |

| |

| nor u5 (zero,sum[0],sum[1],sum[2],sum[3],sum[4]); |

| |

| endmodule |

`------------------------------------------------------'

.2.23 4-

 

4- 1- (fulladd) -. . : fulladd nor. fulladd , nor - Verilog, .

, : 0, 1 2. fulladd . Verilog . , , :

wire [3:0] databus;

 

, , / . adder4 fulladd. .2.24 fulladd.

,------------------------------------------------------.

| module fulladd (in1,in2,arryin,sum,carryout); |

| |

| input in1,in2,carryin; |

| output sum,carryout; |

| |

| assign {carryout,sum} = in1 + in2 + carryin; |

| endmodule |

`------------------------------------------------------'

.2.24 1-

 

 

.2.25 adder4 .

sum fulladd, zero .

,------------------------------------------------------.

| module adder4 (in1,in2,sum,zero); |

| |

| input [3:0] in1; |

| input [3:0] in2; |

| output [4:0] sum; |

| output zero; |

| reg zero; |

| |

| fulladd u1 (in1[0],in2[0], 0,sum[0],c0); |

| fulladd u2 (in1[1],in2[1],c0,sum[1],c1); |

| fulladd u3 (in1[2],in2[2],c1,sum[2],c2); |

| fulladd u4 (in1[3],in2[3],c2,sum[3],sum[4]); |

| |

| always @ sum |

| if (sum == 0) |

| zero = 1; |

| else |

| zero = 0; |

| |

| endmodule |

`------------------------------------------------------'

 

.2.25

 

 

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