BEGIN
IF clk=1 and clkevent and ena THEN .
END IF;
END PROCESS;
-
PROCESS (clk1,clk2)
BEGIN
IF clk1=1 and clk1event THEN
ELSIF clk2=1 and clk2event THEN
Q<=.
END IF;
END PROCESS;
, , variable
PROCESS (clk)
VIRABLE A:bit:
BEGIN A:= < >;
D<=< , a>;
END PROCESS;
, . , , , . .
. , .
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Parallel_to_sequential IS
GENERIC (n:integer:=8);
PORT (clk,load: IN std_logic;
din:IN std_logic_vector (n-1 DOWNTO 0);
dout:OUT std_logic);
END new_del;
ARCHITECTURE test OF Parallel_to_sequential IS
SIGNAL reg: std_logic_vector (n-1 DOWNTO 0);
BEGIN
dout<=reg(n-1);
PROCESS
VARIABLE i: integer n-1 DOWNTO 0;
BEGIN
WAIT UNTIL load='1';
reg<=din; --
j:=0;
WHILE j<n LOOP -- n
WAIT UNTIL clk='1' and not clk'stable;
FOR i IN n-1 DOWNTO 1 LOOP
reg (i)<=reg (i-1);
END LOOP;
reg(0)<='0';
j:=j+1;
END LOOP;
END PROCESS;
END test;
8
: , , .
, . .
[]:
A={ S,X,Y, F, V, s(0) },
S ;
X ;
Y - ;
F ;
V - ;
s(0)- .
S, X, Y , . , ,
S ={ s0,s1,.sp,.sn};
X ={ x0,x1,.xr.sm}.
Y ={ yo,y1,.ys,.yk};
|
|
F N - N-1- :
s(N)= F (s(N-1),y(n,N-1)).
.
(.)
y(N)= V (s(N)); (1)
, . .
. , :
V y(N) =V (s(N-1),y(N-1)), (2)
, ( ).
y(N) =V (s(N),y(N)). (3)
S0 | S1 | S2 | S3 | S0 | S1 | S2 | S3 | |||
X0 | S0 | S1 | S2 | S3 | X0 | Y0 | Y0 | Y0 | Y0 | |
X1 | S1 | S2 | S3 | SO | X1 | Y0 | Y0 | Y0 | Y1 | |
X2 | S3 | S0 | S1 | S2 | X2 | Y2 | Y0 | Y0 | Y0 |
TIPE state IS (S0,S1,S2,S3); TYPE input IS (x0,x1,x2); TYPE output IS (y0,y1,y2); -- SIGNAL x:input; SIGNAL y:output; PROCESS(p_clk, reset) SIGNAL s: state; BEGIN IF reset=1 THEN s<=s0; -- -- elsIf p_clk=1 and p_clkevent then CASE s IS WHEN S0 => IF x=x0 THEN s<=S0; ELSIF (x=x1) THEN s<=S1; ELSE s<=S2; END IF; WHEN S1 => IF x =x0 THEN s<=S1; ELSIF x =x1 THEN s<=S2; ELSE s<=S0; END IF; | WHEN S1 => IF x =x0 THEN s<=S1; ELSIF x =x1 THEN s<=S2; ELSE s<=S0; END IF; WHEN S2 => IF x =x0 THEN s<=S2; ELSIF x =x1 THEN s<=S3; ELSE s<=S1; END IF; WHEN S3 => IF x =x0 THEN s<=S3; ELSIF x =x1 THEN s<=S0; ELSE s<=S2; END IF; END CASE; -- Outp: IF (s = s3 and x=x1) THEN y<=y1; ELSIF (s =s0 and x=x2) THEN y<=y2; ELSE y<=y0; END IF; End if; END PROCESS; |
:
arhitecturemoore ofsystem is
signal b,c: ;
Begin
F1: process (x,S) --
Begin
b<=F1(x,S);
end process;
F2: process (S) --
Begin
Y<=F2(S);
end process;
MEM: process (clock) --
Begin
S<=b; -- S<=F1(x,S),
-- F1
end process;
end moor;
, ,
process (clk,reset)
Begin
if reset=1 then state<=s0;
elsis clk=1 and clkevent then;
Case state is
when s0=> if x=x1 then state<=s1;
elsif x=x2 then state<=s2;
end if;
when s1=> if x=x1 then state<=s0;
elsif x=x2 then state<=s2;
end if;
|
|
when s2=> if x=x2 then state<=s1;
end if;
end case;
end process;
process (S) -- .
Begin
Case state is
when s0|s1=> y<=y0;
when s2=> y<=y1;
end case;
end process;
--y<= y0 when s=s0 or s=s1 else --- !!!!!
-- y1;
end moor;