- () , , .
20-25 :
; ; ; 1-2 c; (, , , ) 20-30 ; 1-2 ; ( ); .
-, , , .
, :
1) ( 1), , , ;
2) , , , ;
3) ;
4) ;
5) - - ;
6) - , ;
7) , - - 2.701-84 . . . 2.709-81 . ;
8) Quartus II Altera - -;
9) , Quartuse II , , .
10) , .
11) 74 - ( , , )
:
. (1)
, :
|
|
=
= =
= = (2)
= = (3)
= = (4)
= . (5)
, (1) (.1). :
. (6)
(2) (6) , .
.
AB | CD | |||
(1) (4) (5) Quartus II (.1). .1 (1); (4); (5). ( , FPGA) APEX20K.
(1) ( ) Quartus II , . Quartus II :
=
= =
= .
Quartus II, ( LUT, Option & Parameter Settings, Technology Mapper LUT) :
A1L6 = A & D & (B $!C) #!A &!D & (B $!C);
A = INPUT();
D = INPUT();
B = INPUT();
C = INPUT();
F = OUTPUT(A1L6);
QQQQ = OUTPUT(A1L6);
MMMM = OUTPUT(A1L6);
APEX ( Product Term) . Quartus II, :
A1P21_p1_out = A & D &!B &!C;
A1P21_p2_out = A & D & B & C;
A1P21 = A1P21_p1_out # A1P21_p2_out # A1P31;
A1P01_p1_out = A & D &!B &!C;
A1P01_p2_out = A & D & B & C;
A1P01 = A1P01_p1_out # A1P01_p2_out # A1P11;
A1P31_p2_out =!A &!D & B & C;
A1P31_p1_out =!A &!D &!B &!C;
A1P31 = A1P31_p2_out # A1P31_p1_out;
A1P11_p2_out =!A &!D & B & C;
A1P11_p1_out =!A &!D &!B &!C;
A1P11 = A1P11_p2_out # A1P11_p1_out;
A = INPUT();
D = INPUT();
B = INPUT();
C = INPUT();
F = OUTPUT(A1P21);
QQQQ = OUTPUT(A1P01);
MMMM = OUTPUT(A1P01);
:
.
.
, Quartuse (2).
, .1, (1), (4) (5) . LUT .
, (-, -), - . -. (3):
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|
. (7)
(7) - .2, . -:
. (8)
(8) - .2, .
(7) (8) Quartus II. Quartus II, ( LUT):
A1L7 = C & B & (D $!A) #!C &!B & (D $!A);
C = INPUT();
B = INPUT();
D = INPUT();
A = INPUT();
FF = OUTPUT(A1L7);
DD = OUTPUT(A1L7);
: .
, .2, .
( APEX) Quartus II (.1). Processings/Simulator Settings Mode Functional. , , (Timing) ( Glitch).
, 1. .3. .1 .3 , .
.1
N | f | ||||||||||
.1. (1) (4) (5) Quartus II
.2. (7) - () (8) - () Quartus II
.3. (1)
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|
N | ||
1. .. . .: , 1990.
2. .. : . .: . , 2003.
3. .., .. . .: , 1990.
4. .. . .: , 1983.
5. .. . .: , 1991.
6. ., . : , , . ., 1985.
7. ., . . ., 1988.