..2013
1
C - -------------
1. - (latch) (Flip Flop?
2. Ȼ ?
3. ?
4. D -
5. ?
----------------------
6. ?
7. D- - ?
8. (post trace &route)?
9. ?
10. D , ?
11. , ModelSim ISIM (. ), ?
---------------------------
12. IS[1-3].
13. ?
14. (behavioral) (post trace) ?
15. () ?
16. () XST?
17. XST ?
18. (place &routing) ?
19. (UCF), ?
20. () IS?
21. ( 10) PLAN AHEAD( )?
22. () iMPACT?
23. ISE Summary report?
24. RTL view Technological view?
---------------------------------
25. LUT Spartan-3?
26. (macrocell) Cool runner?
27. ?
28. , FPGA Spartan-3 ( CPLD COOL RUNNER-2) ?
29. LUT D- ?
30. LUT 4-?
31. CPLD FPGA?
32. D- , 1533?
|
|
|
33. LUT() D- ?
34. D- ?
35. ?
36. , (bechavioral)VHDL- , ?
37. (test bench) D CLK, D- ?
c ==
38. ?
39. ?
40. ?
41. ?
42. bypass ?
2 FPGA
1 ?
2
3
4 ?
5
6 ?
7 1533 1554?
8 +
1 ?
2 RTL-view Technological view?
3 ?
4 - ?
5 ( ?
6 , VHDL , ?
,
1. [7-9] VHDL?
2. , ? . D- .1.
3. STD_LOGIC_1164? ?
4. VHDL?
5. ?
6. FPGA, LUT, SLICE, CLB?
7. - 3 ?
8. VHDL?
9. ISE ?
10. ( ) ?
11. ?
12. ?
|
|
|
13. ?
14. Ȼ 4 0,1,X,Z ( 9- STD_LOGIC_1164).
15. std_logic rezolved., . Ȼ?
16. CPLD FPGA?
17. , - CPLD FPGA ?
18. VHDL D- D- ?
19. , (+) std_logic_vector?.
20. std_logic_1164 std_logic std_ulogic?
21. ISE SYNTHESYS REPORT?
22. ( )
23. ?
24. ?
25 ?
26. VHDL
27. ?
28. VHDL
29.
30. ?.
31. RS ?
VHDL--------------------------------
32. VHDL (), , ?
33. VHDL (signal)<= (variable):=?
34. VHDL ?
35. VHDL PASCAL.
36. VHDL.
37. .
38. VHDL ?
39. (test bench)?
40 - to_X01 ?
41. - if (clk='1' and clk'event) then if rising_edge(clk) then?
,
1) 2 4
2) 2 1
3) RS--
4) -
5) J-K
6) 3
2 CPLD
, . 2 FPG , CPLD.
1. FPGA CPLD
2. FPGA CPLD
3. , FPGA CPLD.
4. CPLD ?
5. CPLD?
6. - FPGA CPLD ?
|
|
|
7. ?
