0,15- - 57 . . 8 . 4 128 64- . 500 1 GFLOPS. 8 5 , , , /, , , (-) . 8 18 ( 288 64- ).
, 500 1 GFLOPS. 32 /, 8 . SX-6 8 GFLOPS.
1. .. , .. . . // : , 1966.
2. K. Batcher. STARAN Parallel Processor System Hardware. NCC, 1974.
3. Reddaway. DAP - A Distributed Array Processor. Proc. of 1 st Annual Symposium on Computer Architecture, IEEE, 1973.
4. W. Hillis. The Connection Machine. The MIT Press, 1985.
5. Cray Research, CRAY-1 Computer System Hardware Reference Manual, Bloomington, Minn., pub. no. 2240004, 1977.
6. G. Bell. Ultracomputers: A Teraflop Before Its Time. Communications of the ACM. Vol. 35, No. 8, August 1992.
7. . . . , 3, 2001.
8. J. Makino, E. Kokubo, T. Fukushige, H. Daisaka. Tops simulation of planetesimals in Uranus-Neptune region on GRAPE-6. Proc. of SC-2002.
9. Programmable Logic Data Book. Xilinx, Xilinx, Inc. 1999.
10. DeHon. The Density Advantage of Configurable Computing. Computer, No. 4. 2000.
11. IEEE Std 1076-1993. VHDL'93. IEEE Standard VHDL Language Reference Manual.
12. .. . . . . . . 1981.
13. .. . . . "". 1991.
14. L. Durbeck, N. Macias. The Cell Matrix: An Architecture for Nanocomputing, www.cellmatrix.com.
15. M. Taylor, J. Kim, J. Miller at al. The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs. IEEE Micro, 2002, Vol. 22, No. 2.
16. Smith D., Hall J., Miyake K. The CAM2000 Chip Architecture. Rutgers University. http://www.cs.rugers.edu/pub/technical-reports.
|
|
17. . . . // .: . 1991.
18. .., .., .., .., .., .., .., .. " ". -1000 . " " 2001, 11(55).
19. .., .., .., .., .., .. 32- RISC- . . . 2, , 1994.
20. . . . .: , 1980.
21. ., . . .: , 1993.
22. 3.Smith D., Hall J., Miyake K. The CAM2000 Chip Architecture. Rutgers University, http://www.cs.rugers.edu/pub/technical-reports.
27. .
, , . , : , . , , .
, . , , . . , , .
, , ( ), , .