5.
5.1.
5.2.
5.3.
5.4.
5.5. ROM, FROM, EPROM
5.6. EEPROM -
5.7.
5.8. .
, (), () , . :
, ; ,
( ) ; , , , , , , .
( ) :
() , -
; , . ( ) , .
() .
, , (MainMemory) ( ) , (, ) (, /, . .). RAM (RandomAccessMemory) . .
, : ( ) , ,
; , -
; ,
, , , .
, (, ).
, , , . ( ) . , , , .
|
|
|
, , .
(accesstime) .
, .
. , .
( ), . (1 I8088; 2 I8086, I80286, I386SX; 4 I386DX, I486; 8 Pentium ). , , . 32- ( ) Pentium , , 64 .
, ( , SIMM DIMM), . . ( ) .
, (bankinterleaving). , ( ) . , () . (twowayinterleaving, threewayinterleaving).
(shadowmemory) ROM BIOS . .
ShadowROM (ROM) RAM RAM, . ShadowRAM (RAM), . Shadow RAM .
, ( ), , . ( ) ( ).
|
|
|
: (ROM BIOS 8 , 8 16 ) (ROM 100 , ).
I486 BurstCycle. . (, , ,...) . , : .
, . , , .
, . , , . .
, ( ). .
() . (Paritybit), . (NMI) ParityErrorCheck ( ) Halt.
Memory (ErrorCheckingandCorrecting). ( , ) , . , BIOS Setup. , :
, ; , ; , (
).
, , - .
DRAM (Dynamic RAM) , , . , , . , , , . , (
|
|
|
) . , ( ). , .
DRAM . (, MultiplexedAddress) . ( ) , (MemoryRefresh ) ( ) . .
, , , , , .
() . PC . , , , .
() , , . ( , ) .
SRAM (StaticRandomAccessMemory), , , . . ( ). . , . . - (CMOS Memory) 100 , , PC. , , . SRAM 1 . SRAM .
|
|
|
. 1.14.
, , CS#, # WE#. CS# (Chipselect). # (OutputEnable) , WE# (WriteEnable) (. 1.14). # ( 1), WE# ( 2). CS# Ȼ , : CSO#, CS1 CS2#.
0, 1, 0 .
. SRAM 12, 15 20 , 2111 (. . ) 66 .
3222.
. : ROM, PROM, EPROM, EEPROM, FlashMemory, , . , , , . , , ROM (ReadOnlyMemory ) ( ).
, . (CMOS Memory CMOS RTC) ; ESCD (ExtendedStaticConfigurationData) , Plug&Play, . . NVRAM (Non-Volatile RAM), .
( ) () . ( ) . , , (). ( , ). . :
