- HDL (Hardware Description Language) , . Verilog, , MaxPlus 2.
, : ( !); .
, , , . (escaped), \ . Verilog (. Help).
- , //.
/* */ - , - .
: ( ), , ( b, o, d, h 2-, 8-, 10-, 16- ) . . .
- (wire) (reg), - 1 . : 0, 1, z, . z , , - , 0 1.
wire , , (driver). wire. wire.
reg , , . reg .
() (Range). , . - (scalared) , . vectored. signed, .
Verilog : . . , , , . , . , .
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, . . wire.
assign (), , , , (, , ).
, . , .
, . 1. , . , .
Verilog : , , .
, . , . , , , .
, . , , ( ~). , , , . . , , d, p1 = &d , , p2 = |d , , p3 = ^d 1, d .
, , . , , . .
, . . , .
: assign q = s? a: b, : if s is true then q = a, else q = b. s , 1 0, b , , .
| assign | = | ? | : | ; |
, , reg, . always, @, , begin - end, , . always () . @ . , , , . , , always. always , begin-end, if case.
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, . posedge, - negedge, positive, negative, edge - .
(blocking) =, . (unblocking procedural) => , .
if , always. - , , . ==. , , , (, 1). , , 0, x, z. , then .
| always | if | ( | ) | ; | else | ; |
case , always, .
, , .
| always | case | ( | ) | 1 | : | ; | ||
| 2 | : | ; | ||||||
| default | : | ; | ||||||
| endcase |
Verilog : , , , . , , .
, . , assign. .
- , , Verilog: and, nand, or, nor, xor, xnor, buf, not (, -, , -, , -, , ). , ( ), : , . :
| ( | , | 1 | , | 2 | , | N | ) | ; |
, , . , , , .
2 1 (.2.1).
1) . (.2.2) , 1.
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2) ( 2.1). - , . .
- 2, module, . , - . , *.v.
3,4. input, , , output - . . ( ) inout.
, wire. wire. wire. ( ), .
- 5. assign . q , (a,b,s). , , . 6, endmodule, .
3) ( 2.2). (. 1). dd1 dd4, y1 y3. 1 - 4 2.1. 5 wire, , . 6 , dd1, 1, - s. 7-9 .
4) ( 2.3), ( 5).
2.1. 2 1.. , , .
1) , ( 1) (.2.2), mux_sch.gdf. .
2) . File/New , Save As mux_var1 .v. Verilog. , Verilog, . , 2.1, File/Project/Set Project To Current File. , Processing Timing SNF Extractor. File/Create Default Symbol.
3) mux_var2, 2.2.
4) mux_var3, 2.3.
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5) , . mux.gdf, (. 2.3), File/Project/Set Project To Current File. , Processing Timing SNF Extractor.
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6) MAX+plus II / Waveform Editor (. 2.4), Save As.
7) Name . Enter Nodes from SNF, List, =>, OK. , .
8) , . a b , s - , , a b.
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a, 12-Clock (. . 1.6), ʻ. , , Options/Grid Size (, 50 ), Clock (100).
b, 12-Clock, Multiplied By 2, ʻ. b , 2 , Clock.
s 4, , 5.
8) MAX+plus II / Simulator, . Waveform Editor File/End Time 1 .
. : s=1 q = , s=0 q = b. ( 4 . 1.6) . , - ..
2.2. . , 4- (. 2.5) 2.3. a,b,q :
input [3:0] a, b;
input s;
output [3:0] q;
, . .
2.3. . ( 2.1), , . 4- (a,b) (q); (cop); (co - Carry Out) (. 2. 6).
. : 0 , 1 , 2 Ȼ, 3 Ȼ.
( 2.4) 2 - . 3 4- a,b, 4 - 2- (cop), 5 (q) 6 (c_o), , , . , , wire, assign, , .
7 , , . , . , , c_o q, . - 5- , , 1, (. . 2.7). , 2.1. . 7 :
assign {p,c_o} = (cop < 2)? (cop==0? (a +b):(a -b)): (cop==2? (a & b):(a ^ b));
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2. 4. . , 1.4, , ( 2.5).
, . . 7, . 2.8.
2.5. 4- , 1.5. . , , 1.5.
2.6. , 1.6.
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1. .
2. Verilog.
3. .
4. assign always, .
5. , .
6. .
7. .
8.
9. .
10. Verilog?
11. .
12. .
13. .
14. .
