, , () Zynq-7000 AP SoC.
Zynq AP SoC ARM Cortex A9 (). :
1. Zynq .
2. (IPs) Zynq , SOC.
Zynq . MIO , . .
1. ISE PlanAhead.
2. Create New Project, New Project wizard.
3. wizarda.
| wizarda | ||
| Project Name | Project name | |
| Project location | . | |
| Create Project Subdirectory | ||
| Project Type | . RTL EDIF | . RTL Project |
| Add Sources | ||
| Add Existing IP | ||
| Add Constraints | ||
| Default Part | Specify | Boards. |
| Board | Zynq-7 ZC702 Evaluation Board. | |
| New Project Summary | Finish |
Finish, New Project wizard PlanAhead.
, Add Sources wizard, . :
1. Add Sources Project Manager. Add Sources wizard.
2. Add or Create Embedded Sources Next.
3. Create Sub-Design.
4. , , system OK. (sources list).
5. Finish.
PlanAhead . , Xilinx Studio (XPS).
XPS.
1. XPS , . .
2. IP Catalog Processor > Processing System, . , , processing_system7 4.03.a .
3. Yes, .
|
|
|
4. Bus Interfaces. , processing_system7.
1.XPS System Assembly View
5. Zynq, -Zynq Processing System.
2.Zynq Processing System
-. , . , .
6. Import Zynq Configurations 
. Zynq.
7. (configuration template) ZC702. , ZC702.
3. Zynq
8. OK.
9. , Zynq MIO Configuration and Design, Yes.
10. -. / .
4. - Zynq
11. Zynq PS MIO Configurations.
12. XPS. PlanAhead .
SDK
SDK PlanAhead.
1. (Sources pane) Design Sources, system(system.xmp) Create Top HDL. PlanAhead system_stub.v .
2. PlanAhead File > Export > Export Hardware for SDK. (Export Hardware).
3. Launch SDK.
4. OK. SDK.
, SDK. system.xml .
5. system.xml SDK
5. SDK.
