6.8. . . . . .
The electron beam is an addressing pointer of high definition and energy density that can easily be deflected. In storage tubes of the 1940's there were severe limitations to such addressing because of the use of surface charge storage and inadequacies in focusing and deflecting the beam. Two recent innovations, storage within a semiconductor and compounded deflection, may bring us closer to realizing the inherent potential of beam addressing.
The addressing is in two parts. First, the beam is deflected by a short conical structure of low aberration and strikes normally one of the appertures of a matrix of lenslets.
The matrix is made up of two metal plates that have an array of holes (an 18 by 18 array on 1.5-mm centres) and are maintained at different potentials. Second, the beam is deflected by bars running along rows and columns between the holes of the matrix. No matter which lenslet is reached, the reduced beam will be subjected to the second deflection. In this compounded deflection the accuracy and stability at each step need only be a small fraction of what would be required with a single step.
6.9. -.
Cache Memory
A cache memory is a small, high-speed system memory that fits between the CPU and the main memory. It accesses copies of the most frequently used main-memory data. When the CPU tries to read data from the main memory, the cache memory will respond first if it has a copy of the requested data. If it doesn't, a normal main-memory cycle will occur.
Cache memories are effective because computer programs spend most of their memory cycles accessing a very small part of the memory.
A cache memory cell has three components: an address memory cell, an address comparator and a data memory cell. The data and address memory cells together record one word of cached data and its corresponding address in main memory. The address comparator checks the address cell contents against the address on the memory address bus. If they match, the contents of the data are placed on the data bus.
An ideal cache memory would have many cache memory cells, each holding a copy of the most frequently used main-memory data. This type of cache memory is called fully associative because access to the data in each memory cell in through the data's associated, stored address.
Not all locations in the memory address space should be cached. Hardware I/O address shouldn't be cached because bits in an I/O register can and must change at any time, and a cache copy of an earlier I/O state may not be valid.
6.19. "Memory Technology". .
Memory Technology
| Type | Predominant Technolog | Cycle or access time |
| Registers and discrete bit storage | Monolithic integrated circuits | 50 to 500 nanoseconds |
| High speed control and scratch-pads | Planar thin films | 100 to 500 nanoseconds |
| High speed internal main memories | Magnetic core | 0.3 to 5 microseconds |
| Random-access auxiliary storage | Magnetic core | 2 to 10 microseconds |
| On-line auxiliary storage | Electromechanical disc files | 15 to 150 milliseconds |
| Off-line auxiliary storage | Magnetic tape serial access | Serial |
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6.20. 'The State-of-art and Future Developments of Memory Technologies".
I. ) , .
) , "Application Fields of Microelectronics: Material Production, Non-productive Sphere, Personal Uses".
II. - .
, :
1. In the world of microelectronics.
2. From the history of microelectronics.
3. The top priorities in the field of microelectronics for the next decade.
4. Prospects of the IC's design.
5. Microprocessors: the state-of-art.
6. The mairi problems the designer of a microelectronic device is faced with nowadays.
7. From the history of Computer Science.
8. Fantastic possibilities of computer and information systems.
9. Progress in the computer revolution.
10. Man-machine systems.
11. Automatic control systems.
12. Systems for computer translation.
13. The advent of minicomputers brings a higher level of information culture.
