, (, ), , .
, , PTD.
PTD5 PTD.
ramstart
| equ
| $0040
| ;
|
romstart
| equ
| $8000
| ;
|
vectorstart
| equ
| $FFDC
|
|
PTD
| equ
| $0003
|
|
DDRD
| equ
| $0007
|
|
| org
| romstart
| ; Flash-
|
| mov
| $20, DDRD
| ; PTD5 D
;
|
loop:
| mov
| $00,PTD
| ;
;
|
| bra
| loop
| ;
|
| end
|
|
|
, - D. EQU . ORG .
mov $20, DDRD PTD5 D . DDRD $20 (%100000).
|
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|
| DDRD7
| DDRD6
| DDRD5
| DDRD4
| DDRD3
| DDRD2
| DDRD1
| DDRD0
|
|
|
|
|
|
|
|
|
|
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|
, PTD5 .
D $00 mov, PTD5 . bra loop, loop, , PTD5 .
. 3.13 .
) )
. 3.13 :
) 1; ) 0
. . 3.14 . 3.15 .
. 3.14.
. 3.15.
2- 7- , . (), 0 3 . . P4 . P5, P6 , , .
, . . 3.16 - 2- 7- .
2- .
romstart:
| equ
| $8000
|
|
ramstart:
| equ
| $0038
|
|
vectorstart:
| equ
| $FFDC
|
|
vectorTIM1
| equ
| $FFF2
|
|
T1SC:
| equ
| $0020
|
|
T1MODh:
| equ
| $0023
|
|
T1MODl:
| equ
| $0024
|
|
PTDPUE:
| equ
| $000A
|
|
DDRC:
| equ
| $0006
|
|
PTC:
| equ
| $0002
|
|
count
| equ
| $0039
| ;
|
rezultat
| equ
| $0053
| ;,
|
syncro
| equ
| $0055
| ;, ; ; 7-
|
syncro+1:
| equ
| $0056
|
|
reserve:
| equ
| $0057
| ; ;
|
odin
| equ
| $0058
| ;, ; ; 7-
|
| org
| romstart
|
|
main1:
| clra
|
| ;
;
|
| clrx
|
|
|
| clr
| count
|
|
| clr
| rezultat
|
|
| clr
| syncro
|
|
| clr
| syncro+1
|
|
| clr
| reserve
|
|
| clr
| odin
|
|
| mov
| #%0100000,syncro
| ;1-
|
| mov
| #%1000000,syncro+1
| ;2-
|
| mov
| #$1,odin
|
|
| mov
| #%1111111,DDRC
| ; PTC
|
| mov
| #$00,PTC
| ;
|
obnulenie:
| mov
| #$0,count
| ;
|
flag:
| bsr
| display
|
|
| inc
| count
| ; 1
|
| lda
| count
|
|
| cmp
| odin
| ; odin
|
| bhi
| obnulenie
| ; 1, count
|
| jmp
| flag
|
|
display:
| lda
| #rezultat
|
|
| add
| count
| ;
;count
|
| tax
|
| ;
|
| lda
| ,x
| ;
;
|
| sta
| reserve
| ; reserve
|
| lda
| #syncro
| ; syncro
|
| add
| count
| ; count
|
| tax
|
|
|
| lda
| ,x
|
|
| add
| reserve
| ; reserve
|
| mov
| #1250,$59
|
|
| sta
| PTC
| ; PTC
|
izo:
| mov
| #%0100110,T1SC
| ; /
|
| mov
| #$FF,T1MODH
|
|
| mov
| #$FF,T1MODL
|
|
| jmp
| *
|
|
prer2:
| dec
| $59
| ; $59 1
|
| bne
| izo
|
|
| mov
| T1SC,$50
| ; /
|
| bclr
| 7,T1SC
|
|
| mov
| #0,PTC
| ;
|
| rts
|
|
|
| rti
|
|
|
| end
|
|
|
, EQU , . . ORG . MAIN , RESET ( Power-on ).
. , . syncro, syncro+1, odin , . . DDRC : %1111111, , . 7- , .
. : , .. . , . . 7- .
(count). DISPLAY, 7- . , bsr DISPLAY, , , odin, .. . , , DISPLAY.
DISPLAY. rezultat. count, H:X. , :, reserve. syncro, count. :. , :. reserve. , , .
100 . TIM08 . PS2 PS1 PS0 T1SC 1 1 0, . . = fbus /64. fbus 68HC908GP32 = 8 . , , , = 125000 . , - 1250 . 2- - . , , , = 125000/1250 = 100 .