AAA ASCII-
AAD ASCII-
AAM ASCII-
AAS ASCII-
ADC
ADD
AND ( )
ARPL
BOUND
BSF
BSR
BSWAP
BT
BTC
BTR
BTS
CALL
CBW
CDO
CLC
CLD
CLI
CLTS
CMC
CMP
CMPXCHG
CMPS
CWD
DAA
DAS
DEC
DIV
ENTER
HLT
IDIV
IMUL
IN
INC
INS
INT
INTO
IRET
INVD -
INVLPG
JECXZ (ECX)=0
JMP
JB (JBNAF) ,
JBE (JNA) ,
JE (JZ) ,
JL (JNGE) ,
JLE (JNG) ,
JLNE (JG) ,
JNB (JAE) ,
JNBE (JA) ,
JNE (JNZ) ,
JNL (JGE) ,
JNO ,
JNP (JPO) ,
JNS ,
JO ,
JP (JPE) ,
JS ,
LAHF AH
LAR
LDS DS
LES ES
LFS FS
LGS GS
LSS SS
LEA
LEAVE
LGDT
LIDT
LLDT
LMSW (MSW)
LOCK
LODS
LOOP
LOOPE (LOOPZ) , ( )
LOOPNE (LOOPNZ) , ( )
LTR
MOV
MOVS
MOVSX
MOVZX
MUL
NEG
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NOP
NOT ( )
OR ( )
OUT
OUTS
POP
POPA
POPF
PUSH
PUSHA
PUSHF
RCL
RCR
REP
REPE (REPZ)
REPNE (REPNZ)
RET
ROL
ROR
SAHF AH
SAL (SHL)
SAR
SBB
SCAS
SET. (16 - . JB:JS)
SGDT GDT
SHR
SHLD
SHRD
SIDT IDT
SLDT LDT
SMSW
STC
STD
STI
STOS
SUB
TEST
VERR
VERW
WAIT
XADD
XCHG
XLAT
XOR
,
FABS
FADD
FADDP
FBLD -
FBSTP -
FCHS
FCLEX SR
FCOM
FCOMP
FCOMPP
FCOS
FDECSTP
FDIV
FDIVP
FDIVR
FDIVRP
FFREE ST
FIADD
FICOM
FICOMP
FIDIV
FIDIVR
FILD
FIMUL
FINCSTP
FINIT FPU
FIST
FISTP
FISUB
FISUBR
FLD
FLD1
FLDCW
FLDENV
FLDL2E log2e
FLDL2T log210
FLDLG2 lg2
FLDLN2 ln2
FLDPL
FLDZ
FMUL
FMULP
FNOP
FPREM
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FPREM1 IEEE-475
FPATAN
FPTAN
FRNDINT
FRSTOR
FSAVE
FSCALE ( )
FSIN
FSINCOS
FSQRT
FST
FSTCW
FCTENV
FSTP
FSTSW
FSTSWAX AX
FSUB
FSUBP
FSUBR
FSUBRP
FTST
FUCOM
FUCOMP
FUCOMPP
FXAM
FXCH
FXTRACT
F2XM1 (2x-1)
FYL2X ylogx
FYL2XP1 ylog (x+1)
FWAIT FPU
2
| AC | |
| ADC | - |
| AS | ( 8 - ) |
| CAN | "Controller Area Network" |
| Ch | (Channel) |
| COP | ( ) -(Computer Operating Properly Watchdog) |
| CPM | CPM RISC- |
| CTM | |
| DTMF | |
| EEPROM | |
| EPROM | |
| Flash | |
| FPU | |
| GPT | |
| I/O | / |
| I2C | Inter-Integrated Circuit |
| IC | (Input Capture), |
| IRAM | |
| IROM | |
| KBI | |
| LCD | |
| LED | |
| LVI | |
| MCCI | - SPI 2SCI |
| MDLC | "Message Data Link Control" |
| MFT | |
| MMU | |
| NI | |
| OC | , |
| PA | |
| PWM | - |
| QSCI | |
| QSM | |
| RRAM | |
| RTC | |
| RTI | |
| SCI | |
| SCI+ | SCI, SPI |
| SIM | |
| SIOP | / |
| SRAM (Static Random Access Memory) | |
| SDRAM (Synchronous DRAM), | . , (Bi-CMOS) 7-10 . |
| SPI | |
| TPU | |
| TPURAM | TPU |
| BEDO (Burst EDO) | . |
| Brainiac | , - |
| CISC (Complicated Instruction Set Computer) | |
| Decoupled architecture ( ). | (decoupled architecture) |
| Direct-mapped cache | - |
| DRAM (Dynamic Random Access Memory) | |
| DSP (Digital Signal Processor) | |
| EDO (Extended Data Output) DRAM | EDO DRAM. , EDO , . |
| FPM (Fast Page Mode) DRAM | . FPM DRAM RAS (Row Address Strobe). , CAS (Column Address Strobe), , . |
| Fully associative cache | - |
| MediaBridge | , I DRAM |
| MediaCodec | - , |
| Mediaprocessor | microunity, . Mediaprocessor , microunity - mediacodec - mediabridge |
| RAM (Random Access Memory) | |
| RISC (Reduced Instruction Set Computer) | . |
| Set-associative cache | - |
| SIMD | |
| SPECint 95, SPECfp 95 | |
| Speed Daemon | . |
| VLIW - | . |
| (Bi-CMOS) | |
| , , , () , () . , , , . | |
| Cray | , RISC-, Cray. . - ( , , , ), , . |
| , (). | |
| , . | |
| , . (Fetch Stage) . 128 . - (Decode Stage) . (Address Calculation) , 1 2. 1 , . 2 , . , 2 . (Execution Stage) . (Write-Back) , /. | |
| Host-processor | |
| MIPS | (Million Instruction Per Second) - |
| MFLOPS | (Million FLOat Point instruction Per Second) - |
| TLB (Translation Look-aside Buffer) | |
| VIS (Visual Instruction Set), | , 64- . |
| MVI (Motion Video Instructions) | , / MPEG-2. |
| ARB | , /, , -. |
| (Branch History Table) | , 256 3- , . 0,8. |
| AGU | |
| PCU |
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