, S-51 ( ). , . 10- - , 256 , 8 28 . . , , "Altera", + PLUSII.
. , - S-51.
:
1) S genei "Altera" ( , CAST) -;
2) S "Triscend" 5, - 8052 FPGA;
3) , S-51 - (, Du812 "Analog Devices" "Altera".
4) S-51 - "Altera".
.
1- , . 8.12. S generic, - ( ) - : (Reg_A, Reg_B, Reg_BD), (Reg_), (RAM) , (vtR). : (OSC), (EEPROM Config), (EEPROM Instuction), (MUX) (ADC). ( ) 2400 2860 , 1050. 80 . , .
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2- (. 8.13), "Triscend", 5 ( 5 EEPROM). 5 - . . , (31.) 5, , . , , -, ( 18 100 . ), , 650 . ( 170 . ).
3- (. 8.14) . ( duC812 "Analog Devices" 10K10 "Altera". duC812 "Anolog Devices" , , , . (EPROM) (S). , , . , . AduC812 "Anolog Devices" 12 .
, 10K10 "Altera" 20 . . , , , 100 . . .
4- (. 8.15) - CS-51 ( 8951 "Atmel" 10K10 . - . . 2- 3- , . S "Triscend".
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. 8.12. S generic
.8.13. S 5
.8.14. DuC812 10K10
.8.15. . 8951 X10K10
1.
:
256 ;
( ) RequstADC, ;
, ReadyData;
ReadyData ;
, ;
(Reg_C);
8- (Reg_A Reg_B) 8- (Reg_C);
. . 8.16. . :
(Data[7..0] ALE ;
WR ( "1" 6- 7- 2 ) 0 1 ;
RD ( "1" 6- 7- 2 ) 0 1 ;
- ; ;
ReadyData.
2.
, (L):
(L_RAM_DQ) 25 8 256 2;
8- (L_COUNTER);
D (L_DFF), 8- .
, , . . 8- , .
, , , , . 8.17. . , + LUS II. (, D- ) . , .
. 8.16. - ,
3.
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, L , , .
- LPM_RAM_DQ (. . ) . -, , . -, .
, , - , . 8.18. - StateCAD Version 3.2 Workview Office "Viewlogic" , , , , .
CntRAM .
.
ReqADC . (StartWr) (StartADC), (ReadyADC), 10 ( WrData) ( WE). , ( IncWr IncAdr). , .
Pause1 ReadyData ( ResAdr),
. . CsADCH CsADCL , , , Rd, IncAdr, . , , . WaitRd, RdByte1, Pause2, RdByte2 .
ReqADC, ReadyADC Rd D-. D- nClock . . ( , Clock), . ReadyData ( ) D-, nClock.
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VHDL- .
StateCAD Version 3.2 Workview Office ( ). , VHDL ( 1).
. 8.18. -
StateCAD , ( ). . - , . Synopsys ( ).
1
VHDL code created by Visual Solution's StateCAD Version 3.2
This VHDL code (for use with Synopsys) was generated using:-enumerated state assignment with structured code format.
Minimization is enabled,implied else is enabled,
and outputs are manually optimized.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY synopsys;
USE synopsys.attributes.all;
ENTITY CntRAM IS
R (CLK,Max,Rd,ReadyADC,Reset:IN std_logic;
IncAdr,ReadyData.ResAdr,StartADC,We:OUT std_logic);
END;
ARCHITECTURE BEHAVIOR OF CntRAM IS
Y type_sreg IS(AdrNew,EndLoop,Idle,IncWr,Pause1, Pause2, Pause3,RdByte1,
RdByte2,StartWr,WaitWr,WrData);
SIGNAL sreg,next_sreg:type_sreg;
BEGIN
PROCESS (CLK)
BEGIN
IF CLK='1' AND CLK'event THEN
IF (Reset='1') THEN
sreg<=idle;
ELSE
sreg<=next_sreg;
END IF;
END IF;
END PROCESS;
PROCESS(sreg,Max,Rd,ReadyADC,ReqADC,Reset)
BEGIN
IncAdr<="0";ReadyData<="0";ResAdr<="0";
StartAdc<="0";We<="0";
next_sreg<=AdrNew;
IF(Reset='1') THEN
next_sreg<=Idle;
IncAdr<='0';ReadyData<='0';StartADC<='0';
We<='0';ResAdr<='1';
ELSE
CASE sreg IS
WHEN AdrNew=>
ResAdr<='0';StartADC<='0';
We<='0';
IncAdr<='1';ReadyData<='1';
next_sreg<=Pause3;
WHEN Idle=>
IncAdr<='0';ReadyData<='0';
StartADC<='0';
We<='0';ResAdr<='1';
IF (ReqADC='1') THEN
next_sreg<=StartWr;
END IF;
WHEN IncWr=>
ReadyData<='0';ResAdr<='0';
StartADC<='0';
We<='0';IncAdr<='0';
IF (Max='0') THEN
next_sreg<=StartWr;
END IF;
IF (Max='1') THEN
next_sreg<=Pause1;
END IF;
WHEN Pause1=>
IncAdr<='0';StartADC<='0';
We<='0';
ResAdr<='1';ReadyData<='1';
next_sreg<=WaitRd;
WHEN Pause2=>
IncAdr<='0';ResAdr<='0';
StartADC<='0';
We<='0';ReadyData<='1';
IF (Rd='0') THEN
next_sreg<=Pause2;
END IF;
F(RD='1') THEN
next_sreg<=RdByte2;
END IF;
WHEN Pause3=>
IncAdr<='0';ResAdr<='0';
StartADC<='0';
We<='0';ReadyData<='1';
IF (Max='1') THEN
next_sreg<=Idle;
END IF;
IF (Max='0') THEN
next_sreg<=WaitRd;
END IF;
WHEN RdByte1=>
IncAdr<='0';ResAdr<='0';
StartADC<='0';
We<='0';ReadyData<='1';
IF (Rd='0') THEN
next_sreg<=Pause2;
END IF;
IF (Rd='1') THEN
next_sreg<=RdByte1;
END IF;
WHEN RdByte2=>
IncAdr<='0';ResAdr<='0';
StartADC<='0';
We<='0';ReadyData<='1';
IF (Rd='0') THEN
next_sreg<=AdrNew;
END IF;
IF (Rd='1') THEN
next_sreg<=RdByte2;
END IF;
WHEN StartWr=>
IncAdr<='0';ResAdr<='0';
StartADC<='1';
We<='0';ReadyData<='0';
IF (ReadyADC='1') THEN
next_sreg<=WrData;
END IF;
IF (ReadyADC='0') THEN
next_sreg<=StartWr;
END IF;
WHEN WaitRd=>
IncAdr<='0';ResAdr<='0';
StartADC<='0';
We<='0';ReadyData<='1';
IF (Rd='1') THEN
next_sreg<=RdByte1;
END IF;
IF (Rd='0') THEN
next_sreg<=WaitRd;
END IF;
WHEN WrData=>
IncAdr<='0';ResAdr<='0';
StartADC<='0';
We<='1';ReadyData<='0';
next_sreg<=IncWr;
WHEN OTHERS=>
END CASE;
END IF;
END PROCESS;
END BEHAVIOR;
VHDL. (IEEE Synopsys). ENIY : (CLK), (), (Rd ReqADC) , (ReadyADC) , , (Reset) (StartADC), (IncAdr,ResAdr), (We) (ReadyData).
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ARCHITECTURA ( ) , ENTITY.
, , , ARCHITECTURA.
type_sreg (, , , ). sreg next_sreg t_sreg. .
(). , CLK. CLK. ( IF CLK='1' AND CLK'event THEN sreg<=next_sreg;END IF;) . ( IF(Reset='1') THEN sreg<=Idle;).
.
, (sreg) - . . VHDL "CASE", . , . next_sreg . , , , , . , .
4.
. ( D- ) FLEX 10K ( SRAM). 8 , . (*.t), , , 10 EPF10K10TC44. ( ) 17%. , 66% . / 62, .
5.
+ PLUS||. . . 8.19. .
0 0,075 . . .
0,075 0,2 . (ReqADC) . ( ).
0,15 0,45 - (StartADC) (ReadyADC), 00 , 2 (, , ).
0,45 1,75 : (CD 3), (F5 1) (7 2) 1, 2 3.
:
0,45 L 8- 55, ;
1,3 4 ( nWR 2_ = 1, 2_7 0, 0 =0 1 = 0);
1,625 9 ( nWR 2_6 = 1, 2_7 = 0, 0 = 1 1 = 0).
1,75 , (ReadyData) . nRD 2_6 2_7 (2,0 2,325), (2,675 3,05), (3,575 3,9), (4,325 4,75), (5,15 5,575), (5,85 6,25), (6,65 6,950) (7,275 7,675) , , .
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ReadyData Idle ( 7,95 ).
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6.
. .
7.
, . , , , 1010. , , , . , . ( ) , . 1010 , (, 1 8 "Altera").
