VERILOG
VERILOG 1985 . (IEEE) IEEE 1364 1994 . [2]. 2 . VHDL, ADA PASCAL, VERILOG , , ( ), , VHDL. IEEE 13642001 (VERILOG-2001), , , , VHDL [15] (. 2). , , . VERILOG-2000 , VERILOG-2001.
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X, z, Z .
verilog , , , , ..
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, , . Verilog . 0 9 . :
<size><baseformat<number>
size , ( , ). , 32 (32 , ). base format , (, ...). ('). : d - ; h - ; - b - . , . number : 0 9 ; 0 7 ; 0 1 ; 0 9 , , , d, , f . , .
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size, number . -8h5A (8h5A), 8h-5A .
number x, X, z, Z
(?) ( size ). X
() , .. .
z Z - z-
(). ? z
, (don't-care).
, : 8b1 8b11111111, 8b01 8b00000001. , ,
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: , 8hB6 8 h B6. number , (_), . 83465 83_465; 8b01100111 8b0110_0111. size number .
Verilog
Verilog - . .
, (signal). , (wire) . . .
Verilog , wire. , , . Verilog:
wire a;
, b , :
wire b;
assign a = b;
:
wire a = b;
:
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wire [3:0] c; //
, . :
wire [3:0] d;
assign c = d; //
.
wire [11:4] e; //
wire [0:255] f; //256-
:
wire g;
assign g = f[2]; // g f
, :
wire [7:0] h;
wire i = f[h]; // i h f
:
wire [3:0] j = e[7:4];
, Verilog, :
wire [7:0] k [0:19]; // 8-
: reg. (behavioral) . () , (wire). , , , , D- D-. D- . D- flipflop.
:
reg [3:0] m;
reg [0:100] n;
, , :
wire [1:0] p = m[2:1];
, (R AM):
reg [7:0] q [0:15]; // 16 , 8
integer. reg, 32 . , :
integer loop_count;
Verilog . (module). , wire.
( ):
module my_module_name (port_a, port_b, w, y, z);
:
input port_a;
output [6:0] port_b;
input [0:4] w;
inout y; // ,
//
, reg, wire:
output [3:0] z;
reg [3:0] z;
:
module my_module
(
input wire port_a,
output wire [6:0]port_b,
input wire [0:4]w,
inout wire y,
output reg [3:0]z
);
, w ire:
wire r = w[1];
, :
assign port_b = h[6:0];
endmodule.
module my_module_name (input wire a, input wire b, output wire c);
assign c = a & b;
endmodule
, :
wire [12:0] s = 12; //32- , 13
wire [12:0] z = 13d12; //13-
wire [3:0] t = 4'b0101; //4-
wire [3:0] q = 8'hA5; //8- A5
wire [63:0] u = 64'hdeadbeefcafebabe; //64-
, 32- . .
. . , 1 aa :
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wire [3:0] aa;
wire [3:0] bb;
assign bb = aa + 1;
Verilog . , , 4.
4
| real | ||
| {} | ||
| + - * / | ||
| % | ||
| > >= < <= | ||
| ! | ||
| && | ||
| || | ||
| == | ||
| != | ||
| === | ||
| !=== | ||
| ~ | ||
| & | ||
| | | ||
| ^ | ||
| {^~ ~^ | ||
| & | ||
| ~& | - | |
| | | ||
| ~| | - | |
| ^ | ||
| ~^ ^~ | ||
| << | ||
| >> | ||
| <<< | ||
| >>> | ||
| ?: |
Verilog :
- + -! ~ ()
- * / %
- + - ()
- << >> <<< >>>
- < <= > >=
- ==!= ===!===
- & ~&
- | ~|
- &&
- ||
- ?:
, ?: .
Verilog 8 3- .
:
Y1=X1vX3vX5vX7
Y2=X2vX3vX6vX7
Y3=X4vX5vX6vX7
Verilog.
1- :
module SHIFRATOR (input X1, input X2, input X3, input X4, input X5,input X6, input X7, output Y1, output Y2, output Y3);
assign Y1=X1|X3|X5|X7;
assign Y2=X2|X3|X6|X7;
assign Y3=X4|X5|X6|X7;
endmodule
2- :
module SHIFRATOR (X1,X2,X3,X4,X5,X6,X7,Y1,Y2,Y3);
input X1,X2,X3,X4,X5,X6,X7;
output Y1,Y2,Y3;
assign Y1=X1|X3|X5|X7;
assign Y2=X2|X3|X6|X7;
assign Y3=X4|X5|X6|X7;
endmodule
, :
1- :
module MULTIPLEXOR (A0, A1, D0, D1, D2, D3, Y);
input A0, A1, D0, D1, D2, D3;
output Y;
assign Y=(D0&!A1&!A0)|(D1&A0)|(D2&A1&!A0)|(D3&A1&A0);
endmodule
2- ( wire):
module MULTIPLEXOR (input A0, input A1, input D0, input D1, input D2, input D3,
output Y);
wire S1, S2, S3, S4, S5, S6;
NOT my_1_not (.OUT(S1),.IN1(A0));
NOT my_2_not (.OUT(S2),.IN1(A1));
AND3 my_1_and (.OUT(S3),.IN1(S1),.IN2(S2),.IN3(D0));
AND2 my_2_and (.OUT(S4),.IN1(A0),.IN2(D1));
AND3 my_3_and (.OUT(S5),.IN1(S1),.IN2(A1),.IN3(D2));
AND3 my_4_and (.OUT(S6),.IN1(A0),.IN2(A1),.IN3(D3));
OR4 my_or (.OUT(Y),.IN1(S3),.IN2(S4),.IN3(S5),.IN4(S6));
endmodule
