. D , . 1.36. S = ST, .
1.36. S
, ; , . , . .
. , . , , , , .
. , . , .
, . D , .
4 . 1.37. 4 D D1 D4. ( 1) . 4 . : , , . .
, .. 0, R .
. : ( ), . ( 1) . , , .
1.37.
1 , S, . , .. 2 2. . .
. ( ). , , , .
|
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.
, . 1.39. . 
1.38. -
1. 39 -
D . . 1.40. D D1. D4 D . , . R - . .
1.40. -
. 1.41 .
1.41.
, , . () .
: D . , D , . 1.42. D1 D3 , D4 D5 . . , D4 1, . . . .
1.42. - D -
.1.43. , . , .
1.43. - , 2 .
( ) . , , , ..
.
1. . , . , . R , 2R .
2. . 0 1; .
|
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3. . , δ - , .
. 1.44
1.44. -
, . , , . . .
, .
1. , . , .. . .
2. .
2 , . , .
, . , , .
- 2. 1000000... []. " ". .
) . . .
) , .
) : 0, , .. . 0 . .
.
1. s 1. , .
2. . , 10000...1 10101...01 .
3. , . : 1011 ; 1101
. . , 10000000... . S 2S - 1, , . . , S , .
. , .
1. S. . 2S , , .
|
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2. . . R , . , , 1 . , . - .
3. - 1000000.... . .
3 XC9572XL
3.1.
XC9572XL - , :
1) CPLD;
2) / ( 10 .);
3) ;
4) ;
5) JTAG;
6) ;
7) ;
8) .
XC9572XL XC9500XL, 1600 (5 ). 54V18 . [7] . 3.1 .
3.1
.3.2
3.2 -
( )
3.2.
3.3 .
3.3
:
- (D1);
- 50 (D2, L1, C1);
- (VD1, R1);
- (C2,C3,C4,C5,D3);
- (1, 2, 3, 4).
3.2.
3.4
3.4.
:
- X1 ;
- X2 ( );
- X3, X4 .
:
- , X1, R1 - R14, VD1, VD2, C1 C5, X2, D1,D2;
- (VT1, VT2,VT3, VT4);
- (VD3, VD4, VD5, VD6, VD7, VD8, VD9, VD10);
- (SW1, SW2, SW3, SW4, SW5, SW6, SW7, SW8);
- (BTN1, BTN2, BTN3, BTN4, BTN5, BTN6).
3.3.
(LD1- P27, LD2- P28, LD3- P29, LD4- P30, LD5- P31, LD6- P32, LD7- P33, LD8- P34.
. 3.5 .
3.5.
(BTN1- P44, BTN2- P43, BTN3- P42, BTN4- P40, BTN5- P41,). VCC3.3 47. , 4.7. 47 - 4.7 (1/10 VCC3.3) . RC - D1. , .
|
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. 3.6 .
3.6.
(SW1- P19, SW2- P18, SW3- P16, SW4- P14, SW5- P36, SW6- P37, SW7- P38, SW8-P39). 4.7 .
.3.7 .
3.7.
(a- P13, b- P22, c- P23, d- P5, e- P12, f- P8, g- P6, dp-P7, A1- P20, A2- P21, A3- P3, A4- P2).
32 (. . 3.8) 8 (, , , CD, CE, CF, CG, DP). 32 4 .
. 
3.8.
.
1
Xilinx ISE Design Suite 14.4.
1. .
1.1. ISE Design Suite 14.4.
. 3.9 ISEDesignSuite 14.4.
3.9 - ISE Design Suite 14.4.
1.2. (. . 3.10) : Project Setting Project.
. 
3.10. - NewProject
1.3. \
. 3.11 Create New Project.
3.11 - Create New Project
1. : Name
2. : Location
3. : Schematic
4. : Next
1.4. : Project Setting
. 3.12 Project Setting
3.12 - Project Setting
1. (Family) :XC9500XLCPLDs.
2. (Device) :XC957XL.
3. (VQ44) XC957XL ().
4. (Speed) .
5. (PreferredLanguage) .
6. (Next).
2.
: Project Summary
. 3.13 Project Summary
3.13. - Project Summary
:Finish
:NewSource
. 3.13 New Source
3.13 - New Source
. 3.14 Select Source Type
3.14 - Select Source Type
Schematic File Name Next→Finish.
3. .
3.1
.3.15
3.15 -
:
1- .
2- .
3- .
4- ().
5- . 6- .
3.2
Add Symbol. . .
.3.16 .
3.16 -
. 3.17 and2.
3/17/ -
, , AddWire .
. 3.18 .
3.18 -
, AddI/OMarker, .
.3.19 AddI/OMarker
3.19. - AddI/OMarker
1. AddName .
2. .
().
3.20 .
, , () () . .
1. () ; Object Properties-Net Attributes.
2. Nets ().
3. New.
4. Attribute value (). ( л, Pin (), ).
|
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5. Ok.
3.20 - .
3.21 . .
1. Design
2., 3. ImplementDesign .
4. Synthesize-XSI .
5. Translate () VHDL.
6. Fit , (XC9572XL).
7. GenerateProgramming - .
8. Manage Configuration Project (IMPACKT) - .
3.21 -
6. .
3.22 .
3.22 -
1. ISEIMPACT.
2. Boundary Scan.
3. InitializeChain - .
4. .
5. Ok.
3. 23
3.23 -
1. Assign New Configuration File.
2. .
3. .
3.24 .
3.24 -
.
2
: . AND2, AND3, AND3B1, NAND2, OR2, NOR2, NOR3, XOR2, XOR4, INV.
1. AND2. : I0, I1-, -. =I0&I1. AND2 1.
1- AND2
| I0 | I1 | O |
| X | ||
| X | ||
2. AND3. : I0, I1, I2-, -. =I0&I1&I2. AND3 2.
2- AND3
| I0 | I1 | I2 | O |
| X | X | ||
| X | X | ||
| X | X | ||
3. AND3B1. : I0, I1, I2-, -. =~I0&I1&I2. AND3B1 3.
3- AND3B1
| I0 | I1 | I2 | O |
| X | X | ||
| X | X | ||
| X | X | ||
4. NAND2. : I0, I1- , - . =~(I0&I1). NAND2 4.
4- NAND2
| I0 | I1 | O |
| X | ||
| X | ||
5. OR2. : I0, I1-, -. =I0│I1. OR2 5.
5- OR2
| I0 | I1 | O |
| X | ||
| X | ||
6. NOR2. : I0, I1-, -. =~(I0│I1). NOR2 6.
6- NOR2
| I0 | I1 | O |
| X | ||
| X | ||
7. NOR3. : I0, I1,I2-, -. =~(I0│I1│I2). NOR3 7.
7- NOR3
| I0 | I1 | I2 | O |
| X | X | ||
| X | X | ||
| X | X | ||
