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t_= t_+ t+ t,
t_- , ;
t- ;
t- , ( , ).
t_= t_+ t+ t,
t_- , ;
t- , ;
t- .
t= max(t_, t_).
, ( ), . , . .
, .
, . , ; ( ).
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. . -.
- .
, .
, , -, , . , . -.
- . , .
- , .
- , , , . , LRU (Least Recently Used ), , . , .
. (LI Cache) 486 ; . (8-32 ). , ( , ). (L2 Cache) 486 Pentium ( ), 6 Pentium 4 , .
- (coherency) - , , (bus master) , (PCI, VLB, ISA . .). , , .
- , , , - .
32- : (LI Cache L2 Cache), (TLB) . ( , ) 486, Pentium, 6 Pentium 4.
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Pentium III L2- 256 , , . Pentium 4 L2- 256 , , 256- .
(DRAM), (wait states). (SRAM), , , , ( ). . DRAM - SRAM.
, . , . (cache directory) . , , .
- , . , - (cache hit), -. , - (cache miss), . , , . , , . , . , ( Look aside). , . : ( Look Through), , , , .
(cache line) . , , , . . (valid) , .
, (.. ), (tag) (tag RAM). ( ), 486 , ( 486 44=16 , Pentium 48=32 ). (sectored) , , . , , . , , , , ( ) .
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, 6 . , , ( ). - , , , (Write Policy). : WT (Write Through) WB (Write Back).
WT ( ), , . . . ( , - , ). . , FIFO- .
WB . , , , , (dirty), , .. . ( ) (clean), . . ( , ) . , , WT. , , , , , . .
-: (direct-mapped cache), (fully associative cache) - (set-associative cache).
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- , , , . 256 32 64 Pentium. . 5.
. 5.
( 256 ), - (256 ). - (, , ) (256 /32= 8 ). , ( . 5 ). , ( ). , , . () - (index). , ( ). , , , , -. , . , . (snoop cycle), (inquire). , , ( ) ( -). -. ( ), . ( ). (read ahead), ( ). .
. , . 5. , , ( ), , (cache trashing). , , .. -. -, . , . , , .
(cached) - (Vcache) (N):
cached=Vcache 2N, cached=256 28= 64 .
(set), . (line) , . ( ) , ( ). , ( ) - (. 6).
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. 6.
-
- , (set). , , , .
(Two Way Set-Associative Cache - ). (. 7).
. 7. -
(), , ( ). , , ( ), . , , , -. , ( LRU Least Recently Used). ( ) Pseudo-LRU (Four Way Set Associative Cache) , 3 . FIFO ( ) (random) , , .
- . , , ( ) .
, . , , () , . - , , - . , . , , . .
