(Tplhc:time:=15 * TD;
.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.m_prims.all;
ENTITY KP1533TM9 IS
GENERIC (Tplhc:time:=15 ns; -- C
Tphlc:time:=17 ns); -- C
PORT (D1: IN std_logic;
D2: IN std_logic;
D3: IN std_logic;
D4: IN std_logic;
D5: IN std_logic;
D6: IN std_logic;
C: IN std_logic;
R1: IN std_logic;
Q1: OUT std_logic;
Q2: OUT std_logic;
Q3: OUT std_logic;
Q4: OUT std_logic;
Q5: OUT std_logic;
Q6: OUT std_logic);
END KP1533TM9;
ARCHITECTURE model OF KP1533TM9 IS
BEGIN
DQFFC_16: m_DQFFC
GENERIC MAP (trise_clk_q=>Tplhc, tfall_clk_q=>Tphlc)
PORT MAP (q=>Q1, d=>D1, clk=>C, cl=>R1);
DQFFC_17: m_DQFFC
GENERIC MAP (trise_clk_q=>Tplhc, tfall_clk_q=>Tphlc)
PORT MAP (q=>Q2, d=>D2, clk=>C, cl=>R1);
DQFFC_18: m_DQFFC
GENERIC MAP (trise_clk_q=>Tplhc, tfall_clk_q=>Tphlc)
PORT MAP (q=>Q3, d=>D3, clk=>C, cl=>R1);
DQFFC_19: m_DQFFC
GENERIC MAP (trise_clk_q=>Tplhc, tfall_clk_q=>Tphlc)
PORT MAP (q=>Q4, d=>D4, clk=>C, cl=>R1);
DQFFC_20: m_DQFFC
GENERIC MAP (trise_clk_q=>Tplhc, tfall_clk_q=>Tphlc)
PORT MAP (q=>Q5, d=>D5, clk=>C, cl=>R1);
DQFFC_21: m_DQFFC
GENERIC MAP (trise_clk_q=>Tplhc, tfall_clk_q=>Tphlc)
PORT MAP (q=>Q6, d=>D6, clk=>C, cl=>R1);
END model;
.
DQFFC_16: m_DQFFC
GENERIC MAP (trise_clk_q=>Tplhc, tfall_clk_q=>Tphlc)
PORT MAP (q=>Q1, d=>D1, clk=>C, cl=>R1);
m_DQFFC m_prims (. m_prims.vhd). - m_DQFFC, m_prims.vhd m_DQFFC.
m_tsb m_prims. m_prims.vhd.
, , VHDL- generate . 22
22 generate
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.m_prims.all;
ENTITY KP1533IR22 IS
GENERIC (Tplh:time:=12 ns;
Tphl:time:=16 ns;
Tpzh:time:=40 ns;
Tpzl:time:=30 ns;
NN: positive:= 8
);
PORT (D0: IN std_logic;
D1: IN std_logic;
D2: IN std_logic;
D3: IN std_logic;
D4: IN std_logic;
D5: IN std_logic;
D6: IN std_logic;
D7: IN std_logic;
C: IN std_logic;
EZ: IN std_logic;
Q0: OUT std_logic;
Q1: OUT std_logic;
Q2: OUT std_logic;
Q3: OUT std_logic;
Q4: OUT std_logic;
Q5: OUT std_logic;
Q6: OUT std_logic;
Q7: OUT std_logic);
END KP1533IR22;
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ARCHITECTURE model OF KP1533IR22 IS
SIGNAL L1: std_logic;
SIGNAL N1: std_logic;
SIGNAL N2: std_logic;
SIGNAL N3: std_logic;
SIGNAL N4: std_logic;
SIGNAL N5: std_logic;
SIGNAL N6: std_logic;
SIGNAL N7: std_logic;
SIGNAL N8: std_logic;
signal N,D,Q: std_logic_vector(1 to NN);
BEGIN
N<=(N1 & N2& N3 & N4 & N5 & N6 & N7 & N8);
(Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7)<=Q;
D<=(D0, D1, D2, D3, D4, D5, D6, D7);
L1 <= NOT (EZ);
G1: for i in 1 to NN generate
DLATCH_3: m_DLATCH
GENERIC MAP (trise_clk_q=>0 ns, tfall_clk_q=>0 ns)
PORT MAP (q=>N(i), d=>D(i), enable=>C);
end generate;
G2: for j in 1 to nn generate
TSB_142: m_TSB
GENERIC MAP (trise_i1_o=>Tphl, tfall_i1_o=>Tplh, tpd_en_o=>Tpzl, Tpd_en_1=>Tpzh)
PORT MAP (O=>Q(j), i1=>N(j), en=>L1);
end generate;
END model;
3 ) ?
:
1) , m_prims.vhd., , 15.vhd,- - WORK,
2) , .
ISIM :
4. ?
, , .
ISe ACTIVE-HDL
.
1. HDL-
2. .
3. .
4
5. .
ISE :
- prim_sh .
. Project> new source >shematics
, SHEMATICS( HDL )- .sch
design,files,libraries,symbol.
kr1533.vhd,
Project>add copy of soure
.
KR1533IR37.vhd
DESIGN UTILITYes CREATE SHEMATICS
sYMBOLS , 3 KR1533IR37.
.
.
- .
-
-wire bus
. - ADD IO Markers-
CHECK DESIGN RULES
Project> new source>vhdl testbench
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