, FIFO TCLK. , , . UART- -.
, = 0, . = 0, =1 CTSS = , . = 0, = 1 CTSS = 1, .
FIFO . TFL FIFO . 1 = 0, - 32 SCC1- 16 SCC-. TFL = 1 - , , UART BISYNC, FIFO 1 . .
RFW FIFO . RFW = 0, 32 . , 32 , SDMA. , HDLC- Ethernet, . FIFO SCd- 32 16 SCC.
RFW = 1 - . 8 , FIFO SCC1 8 , SCC- - 4 . , 8 , 32 . HDLC, HDLC bus, Apple Talk Ethernet.
. TXSY . , .21. TXSY = 0 . TXSY = 1, 8 . , , RSYN = 1, = 0.
SYNL BISYNC- Transparent-- (. 5.17). SYNC1 SYNC2 DSR. . - SCC-.
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(. 5.37) (. 5.18). HDLC-. DSR , LSB - .
TCI , 1, SCC-. TXD , RXD - . , . . . , . . . HDLC, Transparent Ethernet- ( 8 ), .
DPLL. SCC- DPLL (Digital Phase-Locked Loop), / SCC-. / (. 5.38).
RZ: 1 ; 0 - .
NRZI MARK: 1 - ; 0 - ( ) .
NRZI SPACE: 1 - ; 0 - .
FMO: 1 - ; 0 - .
FM1: 1 - ; 0 - .
Manchester: 1 - ; 0 - . , .
Differential Manchester: 1 - . ; 0 - . .
DPLL SCC- GSMR (. 5.19). RENC , TENC - . NRZ SCC-, DPLL .
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5.19
DPLL , TINV = 1, , RINV= 1. . , FM1, FMO, NRZI SPACE, NRZI MARK.
DPLL- , , , . . . , , DPLL . DPLL- , SCC- Ethernet.
DPLL- SCC-. DPLL- SCC-, , . DPLL , BRG-. , 8, 16 32 , . TDCR RDCR GSMR / DPLL (. 5.20). DPLL , , UART, 1. UART 8, 16 32. , TDCR = = RDCR. 8 , 32 / .
DPLL . DPLL . DPLL . , DPLL, , .
EDGE , DPLL . EDGE = 00, RXD , . DPLL , . EDGE = 01, RxD, EDGE = 10 - . EDGE = 10, DPLL- .
GSMR TSNC (. 5.21). DPLL , RXD , . RXD , .
TSNC = 01 , SCC- Apple Talk. , , , .
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DPLL , (preamble), , SYNC- . , 1 0. SCC- . TPL (. 5.22) GSMR, (. 5.23). TPL , SCC- UART.
. 5.24 , , DPLL .
TEND TxD NMSI-. TEND = 0, , . , TxD= 1 ( ). TEND = 1, , TxD, . IDLE.
, DPLL 8 25 , 25 /8 = 3,125 . , , CLKx BRG- 25 , 25 , DPLL 8, 16 32. SCC- SynCLK/2 DPLL, SCC- , DPLL . DPLL (8) 1:2.
SIR-. Serial Infra-RED (SIR). ASYNC HDLC. UART-: 1 -, 8 , 1 -, (. 5.39). 0 3/16 , 1RP GSMR . 1 . IRP 0, 0 (high), IRP = 1, (low). SIR- SCC2. RDCR TDCR GSMR 16, SIR 1.
. , , . , , , - , - / - . SCC- 860 , (glitch) , SCC- . . . ( ) , 0 1 , . , , .
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DPLL , . GSMR GDE.
1, SCC-. 0, , , 6,25 25 .
. SCC- , , CIPR, CIMR CISR.
SCC- , i CIPR (. 5.25), . SCC-, 0 i CIMR. SCC-, CISR 1 i , SCC-. i SCC-.
SCC- CICR (. 5.40). , CICR SCC- /. (, , , d), - .
SCCaP, SCbP, SCcP SCdP , SCC- (. 5.26).
SPS SCC- (. 5.27). SPS = 0, SCC- . SPS = 1, SCC- .
CICR . IEN IEN = 1 , IEN = 0 - .
IPL . 0 , 7 - . IPL = 4.
HP , . . , 11111 (1F), 15 .
. / , .
, 860 13 , (. 5.41, 5.42). , SCC-. SCC- SCCE. SCC- , , SCCE.
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SCC- CIPR. SCC- , SCCE 0. , SCC- CIPR , CIMR.
. SCC- SCCE, . SCCE 1.
SCCM. SCCE SCCM . SCCE 0 , SCC-, .
RXD, . . IDLE- , IDL. , RXD, SCCS.
RXD BREAK BRK SCCE. RXD BREAK ( BREAK- ) BRKs SCCE. RXD BREAK- ( ) .
SCC- -, (underrun), := 1. Transparent- underrun. SPI- underrun slave- .
UART- , , . , R = 1, , RCCR, CCR.
BISYNC- , , RCH. Transparent- .
SCC-, RISC- BD , BSY:= 1. UART- -, - . ( ).
, RX = 1 SCCE . UART- UART SMC- - . Transparent- 10 .
RXF. HDLC ASYNC HDLC , , .
( DDCMP-) RXB , , I = 1 (Interrupt), . . . SPI I2C , , .
. UART- CR = 1, 1, FIFO. CR=0 UART- SMC, , FIFO SCC-. BISYNC- , BCS. SMC, Transparent, , FIFO , , , . , , , , , .
l(lnterrupt), . SPI, FIFO . , , . HDLC ASYNC HDLC , Transparent- - . BISYNC . SPI I2 FIFO , , , .
GLr , DPLL .
GLt , DPLL .
, , BRG-.
GRA , , , GRACEFULL STOP TRANSMIT. , GRA .
( ) RXD HDLC FLG. RXD, SCCS.
, DPLL-, DCC. RXD, SCCS.
SPI-, master, SPISEL master-, multimaster MIME:= 1.
SCC-. . . , parameter RAM (dual-port RAM). BD . , SCC1 200 BD, - 24 BD.
4 (. 5.43), . - , . . (64 -1) . 32- .
BD , (. 5.44). BD BD . BD BD W:= 1. , RISC- .
SDMA- FIFO- . SCC- SDMA-, , - . BD , - . , , SPI PIP, . .
FC1-FC3, . RFCR ( ) TFCR ( ), parameter RAM . , , .
( ). BD F (First) L (Last) - . , / . / , . (underrun), , (overrun busy error), .
BD . RISC- BD . , , , . RISC- . . N N+1 ( ), (overrun) (underrun) . RISC- N+1 N+2 , .
, RISC- , . BD W (Wrap). , BD . 0, BD .
SCC- FIFO FIFO . FIFO , - . 860 - FIFO 16 SCC2-SCC4 32 SCC1. FIFO SMC, SPI I2C . 860 PIP FIFO .
R:= 1 (Ready) . RISC- FIFO . RISC- R:= 0. , . . BD := 1 (Continuous Mode), RISC- , , R = 0.
BD := 1 (Empty). RISC- FIFO . , RISC- := 0 . , , (busy error).
, , := 1. RISC- , . := 1 (Continuous Mode), RISC- , = 0.
I = 1, RISC- , . CPU, . (events) SCC- .
. RISC- R 8-32 . RISC- , , R . R:= 1 BD TOD:= 1 TODR SCC (. 5.45). TOD:= 1 RISC- . TOD = 0.
TOD , . , FIFO . TODR SCC, . TOD:= 1 , , , .
. . 5.28, 5.29.
15- 12- 9 . . 11- 0- . 11 10 . 8- 2- , , . 1 0 ,
.
15- 1- . , , 1 0 , .
, BD.
(Empty) 1 , , . = 0 RISC- .
R (Ready) , . RISC-
(R = 0) .
W (Wrap), 1, RISC-, - , /, BD .
I (Interrupt), 1, / RX RXB
.
CM (Continues Mode), 1, , , R = 0, ,
= 0.
.
(CIS Lost), 1, , = 0 .
CD (Carrier Detect Lost), 1, , = 0 .
OV (Overrun), 1, , FIFO / - SDMA, FIFO .
UN (Underrun), 1, , , , FIFO, SDMA.
.
(Control), 1, , .
(BCS received) 1, (BCS) .
A (Address), 1, , , , - .
AM (Address Match) , : UADD1 ( AM = 1) UADD2 ( AM = 0) .
F (First) L (Last) , , ( F = 1) ( 1 = 1). .
(BCS Enable) 1, BISYNC BCS.
= 0, .
, , .
BR (Break received) 1, BREAK-.
FR (Frame Error) 1, . , UART- -.
PR (Parity Error) 1, /.
ID (IDLE received) 1, IDLE- .
DE (DPLL error) 1, DPLL . , , . - .
LG (Lenght Violation) 1, , / . , .
(Abort received) 1, ABORT- .
NO (Nonoctet Aligned Frame) 1, , 8 .
CR (CRC Error) 1, CRC () BCR.
SH (Short Frame) 1, , , /.
CL (Collision) 1, - .
ME (Multimaster Error) 1, , SPI, master-, SPISEL , .
DL (OLE character error) 1, BISYNC-, , DLE, .
, .
(Preamble) 1, , .
NS (No Stop Bit) 1, UART- , -.
CR (CIS Report) 1, idle . BD. CR = 0, , , , .
( CRC) 1 BD 1_=1, . = 0, . HDLC . .
` ( BCS) 1 BD L=1, BISYNC- . = 0, . idle.
BCR (BCS Reset) 1, BCS . . 0, .
TD (Transmit DLE) 1, BISYNC- DLE.
TR (Transparent Mode) 1, BISYNC- . underrun DLE-SYNC . TR = 0, underrun SYNC.
PAD (Short Frame Padding) 1 L = 1, Ethernet- PAD, . PAD = 0 L = 1, .
Ethernet- ,
DEF (Defer Indication) , .
(Heartbeat) , 20 .
LC (Late Collision) , (56 64) . . Ethernet- 64 , , , , .
RL (Retransmission Limit) , . 16.
RC (Retry Count) , .
CSL (Carrier Sence Lost) , , . . , , .
QMC- .
UB (User Bit) QMC-. , , , , . .
PAD IDLE (0xFF) FLAG (0x7E), . IDLM CHAMR QMC. . PAD = 0, .
PAD FIFO
, , PAD = ( FIFO/ ).
, (PAD+1) .
- . SCC- (parameter RAM), . (- ) SCC-, . (-) SCC- . parameter RAM CPU . , , SCC- .
SCC- . , , . 860 (. 5.30) (offset) parameter RAM SCC base address 0 .
parameter RAM : - ( SCC base+OxOO) - ( SCC base+030). - . 5.31.
RBASE TBASE (RxBD) (TxBD). BD , ( W = 1 BD BD). RBASE TBASE , 8.
SCC- MRBLR, , . , , - , , MRBLR. , , MRBLR. , MRBLR , , SCC- BD, . . BD .
. BD.
RBPTR TBPTR BD . RBASE TBASE , +0x08 (, RBPTR: = RBPTR + 0x08).
RFCR TFCR (. 5.46) SCC. -1 , , , SDMA- , . 1, SDMA .
RFCR TFCR (. 5.31) . , Ethernet, HDLC Transparent .
RISC- . RX-, - SDMA- , / SDMA. Rx - , SDMA. Rx MLBR, - BD .
SCC-. SCC- ( ) , SCC- / , . / .
1. /, SCC ( ) / .
PxPAR , / SCC-. PxDIR (input) (output). PxODR , , , , Z-.
PCPAR, PCDIR, PCODR , SCC-.
2. SCC- TSA, SI. SIGMR TDMa TDMb .
3. SIMODE TDM-, , , SMC- .
4. TDM , SIRAM SICMR.
5. SCC- NMSI, SICR.
6. GSMR DPLL, 16/32- , , , , FIFO- , . SCC-, ENT ENR .
7. PSMR.
8. , DSR SYNC- .
9. - SCC- - .
10. SCC- SCCE, , / .
11. SCC- SCCM .
12. CICR SCC-. , 0.
13. SCC- CIMR- .
14. CIPR .
15. ENT = ENR= 1 GSMR, SCC-.
16. SCC- , , . , . , , , .
SCC- .
1. ( ) ENR= 0 GSMR. .
2. SCC-. , INIT RX PARAMETERS.
3. , , . ENTER HUNT MODE. BD, RBPTR SCC-, ( = 1). ENTER HUNT MODE , SCC- INIT RX PARAMETERS.
4. ENR:= 1 GSMR, .
SCC- .
1. , STOP TRANSMIT .
2. ( ) ENT = 0 GSMR_L. .
3. SCC-. , INIT TX PARAMETERS. INIT TX PARAMETERS , RESTART TRANSMIT.
4. ENT:= 1 GSMR_L, , TBPTR.
, SCC-, .
1. SCC- ENT = ENR = 0.
2. INIT TX and RX PARAMETERS. GSMR .
3. ENR = ENT:= 1, SCC- .
. ENR ENT SCC- ,